Abstract: System and method for delivery of an electronic message from a sender unknown to a recipient when such message comprises a sender code verified by recipient's electronic message handler, thereby eliminating delivery of unsolicited bulk messages. Dispensing sender codes per recipient addresses thwarts senders of unsolicited bulk messages. Dispensing sender codes upon successful response to a human response question further thwarts bulk senders. Sender code calculation according to periodically changing factors limits sender code utility to finite time periods.

Abstract: For use in verifying the identity of a user, an identity verifier comprising an optical fingerprint sensor coupled to an ID (identification) card reader. In one embodiment of the present invention, the optical fingerprint sensor includes a light source on a PCB assembly, a diffuser that receives light from the light source, a right angle prism that receives light from the diffuser, a collimating lens that receives light from the prism, a first mirror that receives light from the collimating lens, a second mirror that receives light from the first mirror, a third mirror that receives light from the second mirror, an imaging lens that receives light from the third mirror, and an image sensor on the same PCB assembly as the light source that receives light from the imaging lens.

Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical devices such as the core of an optical waveguide or a light scatterer will damage the devices and prevent the passage of light through those sections of the devices. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Abstract: Optoelectronic devices of the present invention include several embodiments of an electronically active optical waveguide made of a strip loaded waveguide with a lateral, self-aligned diode fabricated in a layer of silicon. A voltage applied across the diode changes the free carrier density in a portion of the active waveguide, which can change the refractive index in that portion of the waveguide. Changing the refractive index can cause a phase shift of an optical signal propagating down the waveguide and this effect can be used to control the optical signal. Changing the free carrier density can also change the amount of optical attenuation in a section of an active waveguide. Optoelectronic devices such as: modulators, attenuators, switches, beam diverters, tunable filters and other devices can be fabricated on a standard SOI substrate (silicon on insulator), which is typically used in the fabrication of CMOS integrated circuits.

Abstract: The present I/O ports comprise (1) a layered structure comprising (a) an unpatterned superstrate having at least one layer, (b) an unpatterned substrate having at least one layer, and (c) at least one intermediate layer sandwiched between the unpatterned superstrate and the unpatterned substrate, (2) a coupling region that is within the at least one intermediate layer and that comprises an arrangement of at least one optical scattering element and (3) at least one output waveguide. The present I/O ports can be effectively used in balanced photonic circuits and unbalanced photonic circuits.

Abstract: A treemap with cells that have a minimum size so that large data sets can be clearly represented. A treemap that represents a plurality of data elements is generated, the treemap including a plurality of two-dimensional cells. Each cell represents a corresponding data element in the data set. The treemap includes a portion of a display screen assigned to a first cell so that the first cell has a size. A portion of the display screen is then assigned to a subsequent cell. The size of the first cell is adjusted in order to compensate for a size of the subsequent cell and to maintain the minimum cell size.

Abstract: An automatic white balancing method and system. A modification of “color in perspective” white balancing technique is implemented. Rather than a default projection plane used by the typical white balancing technique, the projection plane for a RGB space is automatically selected to allows the projected reference gamuts in the projection plane to be as disjoined as possible, thereby making them as uncorrelated as possible. In turn, automatic white balancing is performed using the color temperature associated with the projected reference gamut most correlated with the projected gamut of an image sensor.

Abstract: A standard CMOS process is used to fabricate optical and electronic devices at the same time on a monolithic integrated circuit. In the process, a layer of metallic salicide can be depsoited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into the core of an optical waveguide will damage the waveguide and prevent the passage of light through that section of the waveguide. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Abstract: A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG. 6 shows a polysilicon and silicon dioxide light scattering element formed on a silicon waveguide. The polysilicon light scatterer is formed on the core of the waveguide with a silicon dioxide layer between the polysilicon and the core. A standard CMOS process is used to form the waveguide and the light scattering element. FIG. 6A is a table summarizing the elements of the light scatterer and the waveguide of FIG. 6 and the CMOS transistors of FIGS. 1 and 2, which are formed from the same materials at the same time on the same substrate. Forming multiple light scatterers on the core of a waveguide can make a grating coupler.

Abstract: The invention discloses an analog content addressable memory (CAM) that employs analog storage cells with programmable analog transfer function capability. The analog CAM scans and/or compares its memory array contents to determine if an analog voltage applied at Vin matches a value stored in the memory array. If the value applied to Vin matches a value stored in the analog CAM, the analog data stored at a different and corresponding location in an analog storage cell is coupled to the Vout output. An analog content addressable memory, comprising a first array A of analog memory cells for storing and generating a VA voltage; and a comparator having a first input for receiving a Vin voltage, a second input for receiving the VA voltage from the first array A of analog memory cells. Analog-to-Digital and Digital-to-Analog Converters comprising an array of analog memory cells.

Abstract: Apparatus and method for respiratory drug delivery using cartridge containing drug and propellant. User inserts cartridge into body of apparatus and activates piercing trigger to pierce drug compartment and propellant compartment, resulting in mixing and de-agglomeration of drug for respiratory delivery.

Abstract: Internet-based software and associated database provide group analysis overlay to monitor client-server web traffic and provide direct marketing to client group. Client car, patient, office or school sensor and interface provides overlay attribute for database comparison to classify usage pattern, location, timing, or family for targeted messaging for enhanced service from server source. Database group registry tracks client classification and provides adaptive context mapping according to set attribute relative to targeted on-line transaction.

Abstract: Multi-sensor system for real-time embedded monitoring of object senses mixed-mode object conditions. Various sensors separately provide disparate analog signals representing different measurable attributes regarding sensed object. For example, such sensors may separately sense temperature, pressure, or other biometric value. Then, according to specified rule set or other qualifying parameters, a digital signal is generated by a processor or controller to indicate one or more condition of the sensed object according to certain sensor input values. Additionally, such multi-sensor scheme may be coupled to a digital network or otherwise coupled thereto for simulation and/or communication applications.

Abstract: A system and methods for accessing 2D digital images and 3D geometric models over a network (preferably the Internet) and transforming and composing that media along with 2D digital image and 3D geometric model media, acquired by other means, into enhanced 2D image and 3D model representations for virtual reality visualization and simulation is disclosed. Digital images and models from a network and other sources are incorporated and manipulated through an interactive graphical user interface. A photogrammetric media processing engine automatically extracts virtual sensor (camera) and geometric models from imagery. Extracted information is used by a reconstruction processor to automatically and realistically compose images and models. A rendering system provides real-time visualization and simulation of the constructed media. A client-server processing model for deployment of the media processing engine system over a network is disclosed.

Abstract: Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.

Abstract: Local emergency alert service for cell-phone or pager users is provided using regional or localized broadcast to or polling of available, voluntary, or otherwise identified wireless communication devices or other network-accessible nodes operating using different protocol in proximate help area, thus allowing such alerted users to respond to nearby emergency request or condition. Wireless communicator location is determined using relative satellite positioning, radio signal triangulation, or manual entry technique. Sensor may alert wireless communicator automatically of emergency condition.

Abstract: Computer-aided design and manufacture software and hardware automate garment and fashion definition and production. Configurable garment includes ornamental element, pattern display, and personal identifier and wireless sensor electronics.

Abstract: An integrated circuit with improved testability includes a test logic component that replaces a corresponding regular logic component and that generates a logic high or low whenever a test input is activated. Alternatively, it may generate either high or low depending on which of two test inputs is activated. A test program may be augmented with instructions to activate such test inputs. An integrated circuit design may be analyzed to select a node that is not covered by a test program and to identify which logic component generates an output on the node. Then the design may be altered to replace the identified logic component with a corresponding test logic component. Test coverage analysis may be based on determining whether the test program toggles the node, or determining whether a stuck at fault on the node propagates so as to be observed.

Abstract: A method and apparatus for improving the performance of an edge launch electrical connector. Two or more edge vias are established along an edge face of a planar circuit module, such as a single- or multi-layer PCB, integrated circuit on a ceramic or organic substrate or a ceramic or organic package, thereby providing a short path from one or more of the substrate assembly's ground planes to a ground associated with the edge launch electrical connector, reducing jitter and providing a solution with low insertion and return losses. The two edge vias may be standard vias, castellations or wires or lines deposited, printed, painted, secured or put in contact with an edge face of the planar circuit module and are arranged at each side of the signal line thereby providing additional electromagnetic shielding. Optionally, an air line may be established to increase the operational cut-off frequency and/or improve electrical performance.

Abstract: A process for creating a broadly tunable Distributed Bragg Reflector (DBR) with a reduced recombination rate. According to the current invention, this may be achieved by creating electron confinement regions and hole confinement regions in the waveguide of the DBR. Preferably, this is achieved by engineering the band gaps of the DBR waveguide and cladding materials. Preferably, the materials selected for use in the DBR may be lattice matched. Alternately, two or more thin electron confinement regions and two or more thin hole confinement regions may be created to take advantage of strain compensation in thinner layers thereby broadening the choices of materials appropriate for use in creating a broadly tunable DBR. Alternately, graded materials and/or graded interfaces may be created according to alternate processes according to the current invention to provide effective electron and/or hole confinement regions in various DBR designs.