Patents Represented by Attorney Finnegan, et al.
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Patent number: 8063683Abstract: A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of current source circuits, and the current source circuits comprise a plurality of transistors, and the transistors of the current source circuits are coupled to one another by the drains of the transistors.Type: GrantFiled: June 8, 2009Date of Patent: November 22, 2011Assignee: Integrated Device Technology, Inc.Inventors: Hui Wang, Lixin Jiang, Yehui Sun
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Patent number: 7702061Abstract: A multi-bit counter is provided. The multi-bit counter includes a plurality of asynchronous base counter cells coupled in series, the asynchronous base counter cells having a plurality of input terminals. The multi-bit counter also includes at least one logic gate coupled to at least one of the input terminals of at least one of the plurality of asynchronous base counter cells, a reload signal being input into the asynchronous base counter cells, a clock signal being input into the asynchronous base counter cells, and an input voltage being input into the asynchronous base counter cells, wherein the multi-bit counter is synchronous with the clock signal.Type: GrantFiled: December 17, 2007Date of Patent: April 20, 2010Assignee: Integrated Device Technology, Inc.Inventors: Zhuyan Shao, Juan Qiao
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Patent number: 7644311Abstract: A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.Type: GrantFiled: March 31, 2006Date of Patent: January 5, 2010Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Pao-Lu Louis Huang
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Patent number: 7598775Abstract: A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced.Type: GrantFiled: December 19, 2007Date of Patent: October 6, 2009Assignee: Integrated Device Technology, inc.Inventors: Pengfei Hu, Juan Qiao, Zhongyuan Chang
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Patent number: 7594149Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.Type: GrantFiled: May 31, 2005Date of Patent: September 22, 2009Assignee: Integrated Device Technology, Inc.Inventor: David J. Pilling
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Patent number: 7590025Abstract: A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.Type: GrantFiled: December 19, 2007Date of Patent: September 15, 2009Assignee: Integrated Device Technology, Inc.Inventors: Yong Wang, Liang Zhang, Xin Liu
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Patent number: 4586586Abstract: A novel work-step attachment for an extension ladder is described. The work-step attachment generally comprises a platform which is secured to a ladder segment having two vertical side frames in parallel relationship and at least one horizontal rung extending therebetween. The work-step attachment also comprises a hooking element adapted to engage a rung of an extension ladder, as well as a locking element to lock the platform in a first position in which it is aligned with the rung of the ladder segment and in a second position in which it is substantially aligned in the plane of the parallel side frames of the ladder segment.Type: GrantFiled: August 13, 1985Date of Patent: May 6, 1986Inventor: Carlos Canals
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Patent number: 4581142Abstract: A cyclone separator or hydrocyclone with good separation efficiency and large capacity comprises a substantially cylindrical or slightly conical hollow body (1), the lower part of which terminates in an outlet opening (6) for liquid enriched with respect to solid particles, and in which the outlet (7) for purified liquid is defined between a centrally arranged body (11) and a guiding tube (2), and in which the liquid to be purified is introduced via a particularly designed nozzle (13).Type: GrantFiled: September 6, 1984Date of Patent: April 8, 1986Assignee: Titech, Joh. H. AndresenInventors: Tron-Halvard Fladby, Leif N. Hovind
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Patent number: 4561869Abstract: A cryogenic process for removing acid gases from natural or synthesis gases, comprising the following stages:(a) feeding the natural or synthesis gas to a first absorption column in order to absorb the H.sub.2 S;(b) cooling the substantially H.sub.2 S-free gas to condense part of the CO.sub.2 contained in said gas;(c) feeding the cooled and partly condensed gas to a second absorption column in order to reduce the CO.sub.2 content to the required value;(d) regenerating the solvent or solvents used in the acid gas absorption, the solvent or solvents used being chosen from esters, alcohols or ethers, of low molecular weight.Type: GrantFiled: December 27, 1983Date of Patent: December 31, 1985Assignee: Snamprogetti, S.p.A.Inventors: Luigi Gazzi, Roberto D'Ambra, Roberto Di Cintio, Carlo Rescalli, Alessandro Vetere
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Patent number: 4459187Abstract: A process for recovering power is disclosed, by which excess electric power is exploited for electrolyzing alkali metal hydroxides (molten) and the thusly obtained pure alkali metals are stored. When the demand of electric power becomes critical, the alkali metals are reconverted into their hydroxides and the reaction heat, along with the hydrogen produced in the reaction, is recovered to produce steam: the latter can be used either to produce electricity, or to use its heat, or both.Type: GrantFiled: May 16, 1980Date of Patent: July 10, 1984Assignee: Snamprogetti, S.p.A.Inventors: Vincenzo Lagana, Francesco Saviano, Giorgio Fusco
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Patent number: 4451334Abstract: A thermally driven multi-effect distillation process and apparatus are disclosed in which liquid is introduced into a plurality of evaporating and condensing stages or chambers while heat energy is passed through the stages or chambers in a direction countercurrent to the direction of flow of the liquid which undergoes evaporation to form condensate and distilland in each stage or chamber while transferring the heat of condensation to the next downstream stage or chamber and maintaining a minimum temperature differential between stages or chambers, and separately removing condensate and distilland from each stage or chamber while rotating the stages or chambers about an axis passing through the points of introduction thereto of the liquid and heat energy.Generally the apparatus comprises a plurality of adjacent evaporation and condensation chambers and means for introducing liquid and heat energy thereto in countercurrent directions.Type: GrantFiled: November 10, 1981Date of Patent: May 29, 1984Assignee: Grumman Allied Industries, Inc.Inventors: Joseph A. Ciocca, Gregory W. Knowles