Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

Abstract: Consistent with the present invention, there is provided a circuit for extracting a common mode voltage of an input signal. The device may include an operational amplifier having an output, at least one negative input and at least one positive input, a first transistor, and a second transistor. A terminal of the first transistor may be coupled to the output of the operational amplifier. A terminal of the second transistor may be coupled to a terminal of the first transistor and the at least one positive input of the operational amplifier to create a negative feedback loop. The device may further include a common mode output, wherein the negative feedback loop extracts the common mode voltage of the input signal, the common mode voltage of the input signal being output at the common mode output. The device consistent with the present invention may provide the common mode voltage of the input signal without using any resistors, and while only occupying a small die area.

Abstract: A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching.

Abstract: Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common VSSsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.

Abstract: A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.

Abstract: A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

Abstract: The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

Abstract: An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor. The gate of the third transistor is coupled to ground. The gates of the first and the second transistor are coupled to a control circuit that is adapted to provide a control signal to turn the first and the second transistor on or off.

Abstract: A collision detection circuit for a multi-port memory system is presented. The collision detection circuit detects a collision condition if the addresses at two or more ports at the same time match and if one of the two or more ports is writing to the memory location associated with that address. A collision flag can then be set when the collision condition exists. In some embodiments, arbitration can occur when the collision flag is set.

Abstract: The present invention relates to methods for detecting a change in chromosomal structure. These methods employ labeled probes that bind nucleic acids. For example, these probes may be comprised of nucleic acids or nucleic acid analogs and a detectable label.

Abstract: A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.

Abstract: A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception.

Abstract: A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial data input in a first processing unit, generating a data packet based on the serial data input, transmitting the data packet to a first random access memory device via a write input port, decoding the data packet, determining whether to perform a command in the first random access memory device based on information in the data packet, and transmitting the data packet to a second random access memory device.

Abstract: Circuits are disclosed for protecting internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge (EDS). One example circuit includes a trigger circuit including a transistor and a capacitor arranged in series between DC pads. The trigger circuit generates a trigger signal to a discharge circuit connected between the DC pads to shunt charge from one of the DC pads to the other. The RC delay associated with the transistor and capacitor of the trigger circuit may be designed such that the trigger circuit generates the trigger signal in response to an ESD event, but not in response to high positive spikes on one of the DC pads during normal operation.

Abstract: An ATM switch according to the present invention includes a memory and a control circuit. The ATM switch generates a connection table in a memory, generates a multicast master entry including a limit field and a count field. The multicast master entry also includes address locations at which multicast ATM cells are stored. The ATM switch further generates one or more multicast member entries associated with said multicast master entry in said connection table, each multicast member entry identifying a destination connection on which said multicast ATM cells are to be transmitted. Further, the count field is initialized and the limit field is set at a predetermined value. The master entry is then determined to be active or inactive depending on a comparison between the count field and the limit field.

Abstract: Methods and systems are provided for communicating data from wireline terminals to mobile terminals in a telecommunications network, which includes a home node associated with the mobile terminal and one or more visited nodes. To establish communication with a mobile terminal, a wireline terminal sends data to a server in the telecommunications network. The server identifies a mobile identification number associated with the mobile terminal, and based on the identified mobile identification number, the server determines a route that excludes the home node when the mobile terminal is out of the geographical area served by the home node. The server then establishes via the determined route a connection to the mobile terminal and sends to the mobile terminal the data received from the wireline terminal.

Abstract: A method and apparatus is disclosed for improving the security of computer networks by providing a means operating passively on the network for detecting, reporting and responding to intruders. The system is comprised of a plurality of intruder sensor client computers and associated event correlation engines. Resident in the memory of the client computer and operating in the background is a Tactical Internet Device Protection (TIDP) component consisting of a passive intruder detector and a security Management Information Base (MIB). The passive intruder detector component of the TIDP passively monitors operations performed on the client computer and emits a Simple Network Management Protocol (SNMP) trap to an event correlation engine when it identifies a suspected intruder. The event correlation engine, through the use of a behavior model loaded in its memory, determines whether the user's activities are innocent or those of a perspective intruder.

Abstract: A system (100) for mapping an underground object (145) includes a conduit location recording device 105 and a server (115). The conduit location recording device (105) senses an underground object (145), a unique identifier being associated with the sensed underground object (145), and determines a location of the underground object (145). The conduit location recording device (105) transmits, via a communications network (125), the unique identifier and determined location to the server (115) for storage in a database.