Abstract: An image processor in which input image data is sampled at a sampling circuit at a constant rate corresponding to P times the rate of the input image data and then subjected at a decimating circuit 14 to a decimating/reducing operation with a magnification of 1/Q to obtain image data having a magnification of P/Q in a horizontal scanning direction. An original-document reading motor is controlled under a scanner controller so that a relative moving speed between an image and a CCD is set to be lower than an ordinary moving rate. Under this condition, the image is repetitively read a plurality of times with respect to an identical line and then subjected at a line decimating circuit to a decimating/reducing operation on every line basis to obtain a resultant image having a desired magnification in a vertical scanning direction.