Patents Represented by Law Firm Finnegan, Henderson, Henderson, Farabow, Garrett and Dunner
  • Patent number: 5014109
    Abstract: The present invention provides a semiconductor device, comprising a substrate, a first insulation layer formed on the substrate, a first wiring layer formed on the first insulation layer, a second insulation layer formed on the first wiring layer and having a contact hole, and a third insulation layer formed on the second insulation layer, said third insulation layer being in contact with the first wiring layer via the contact hole.
    Type: Grant
    Filed: August 1, 1989
    Date of Patent: May 7, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayoshi Higuchi