Patents Represented by Attorney, Agent or Law Firm Finngean, Henderson, Farabow, Garrett & Dunner, L.L.P.
  • Patent number: 6465842
    Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazumi Nishinohara