Abstract: A latch-up pulse generator system includes a latch-up pulse generator coupled to first and second power supplies, for outputting JEDEC-standardized first and second output pulse trains. The generator includes a master clock, digital frequency dividers, and digitally controlled delay circuitry for outputting the two pulse trains. The first pulse train is a square-wave signal with a repetition rate of about two seconds. The second pulse train has a pulse width that is digitally controllable between about 0.2 .mu.s and 5 .mu.s. The delay between the fall-time of the second pulse train and the fall-time of the first pulse train is variably controlled between about 1 .mu.s and one second in 1 .mu.s steps. The amplitude and current output of each pulse train may range from 0 to perhaps 15 VDC at a current level of about 5 A. For power pin latch-up testing, the two pulse trains are combined to produce a composite pulse train. Signal and/or power pins of a CMOS device under test may be analyzed.