Abstract: An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.
Type:
Grant
Filed:
June 6, 1999
Date of Patent:
November 21, 2000
Assignee:
Lattice Semiconductor Corporation
Inventors:
Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger, Kerry A. Ilgenstein