Patents Represented by Attorney Fletcher Yoder
  • Patent number: 6222257
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: April 24, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6221542
    Abstract: A photomask for manufacturing a semiconductor device. The photomask is manufactured by a providing a photomask substrate and alternately depositing a plurality of layers of a light-absorbing material and of an etch-stop material on the photomask substrate. The light-absorbing material is selected as having a well-defined etching selectivity from that of the etch-stop material. The layers are successively patterned by removing by a selective etching process at least a portion of at least one of said layers, the portion removed from a lower, in relation to the substrate, layer a subset of the portion removed from a higher layer. Together, the patterned layers are used as a photomask to photolithographically imprint a pattern of a photoresist on a semiconductor wafer under manufacture. The photoresist is used in the etching process of the semiconductor wafer.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: April 24, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Alan R. Reinberg
  • Patent number: 6219908
    Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: April 24, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren Farnworth, Alan Wood
  • Patent number: 6218089
    Abstract: Photolithographic methods and apparatus for reducing or eliminating the proximity effect. Multiple exposures using different exposure parameters are used to reduce or to eliminate the proximity effect.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: April 17, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 6213202
    Abstract: A connector permits separation of a submergible pumping system from its deployment system. The connector includes an upper assembly and a lower assembly that are connected by shear screws. A hydraulic separation mechanism is used to shear the shear screws and separate the upper and lower assemblies from a remote location.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: April 10, 2001
    Assignee: Camco International, Inc.
    Inventor: Dennis M. Read, Jr.
  • Patent number: 6216216
    Abstract: In a multiprocessor computer system, a method and apparatus for partitioning the processors therein. The host processors are partitioned, leaving at least one host processor for providing operating system functions, and allocating one or more target processors to perform other functions such as those of a typical IOP. The processors are first allocated and then totally controlled by placing the allocated processors under the control of an application-specific software rather than leaving them under the direct control of the operating system.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: April 10, 2001
    Assignee: Compaq Computer Corporation
    Inventor: Thomas J. Bonola
  • Patent number: 6214726
    Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: April 10, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung T. Doan
  • Patent number: 6212606
    Abstract: A computer system and method using a standardized shareability scheme for establishing a shared level for each of a plurality of storage units located in the computer system. The computer system includes a plurality of hosts and controllers coupled to a peer network (storage area network). Each storage unit is coupled to one of the controllers and includes at least one parametric from a group of parametrics used in classifying the shared level of a particular storage unit. The hosts using the standardized shared levels are able to identify a shareability characteristic of each storage unit.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: April 3, 2001
    Assignee: Compaq Computer Corporation
    Inventor: John E. Dimitroff
  • Patent number: 6212256
    Abstract: A system for managing replacement of x-ray tubes, such as in medical diagnostic systems, includes circuitry for monitoring operating parameters of the x-ray tubes, and circuitry for analyzing the monitored parameters and scheduling for tube replacement based upon predicted failure. The scheduling circuitry may be located in a remote service center and is linked to the diagnostic systems via a network connection. A failure prediction circuit may be located at the remote service center or local to the diagnostic system. Upon identifying a predicted tube failure, replacement of the tube is scheduled and shipment of a replacement tube is ordered. Service personnel may be notified automatically to coordinate tube replacement. Electronic messages may be transmitted to the service personnel and to personnel in the facility where the x-ray tube is installed to notify all parties of the scheduled tube replacement.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: April 3, 2001
    Assignee: GE Medical Global Technology Company, LLC
    Inventors: Diane Marie Miesbauer, Hubert Anthony Zettel, David Lee Southgate, Steven John Fleming
  • Patent number: 6212587
    Abstract: A system for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which in conjunction with the device proxy agent, assigns the memory space assigned to the device proxy agent to hidden devices. A section of memory is allocated as memory address space for the computer bus. A first portion of the allocated memory address space is assigned to non-hidden computing devices and a second portion of the allocated memory address space is assigned to the device proxy agent. The IOP in conjunction with the device proxy agent assigns the memory address space assigned to the device proxy agent to the hidden devices.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: April 3, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Theodore F. Emerson, Christopher J. McCarty
  • Patent number: 6208763
    Abstract: Pixel data representative of a discrete pixel image is processed to identify structures and non-structures in the image defined by the pixel data. The structures and non-structures are processed in different manners. The structures are identified by computing gradient information on each pixel and by comparing the gradient information to a gradient threshold, and by comparing gradient directions for adjacent pixels to one another. The edges defining the structures are binary rank order filtered. The structures are orientation smoothed and sharpened. The non-structures are homogenization smoothed and original texture is blended back into non-structural regions.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: March 27, 2001
    Assignee: General Electric Company
    Inventor: Gopal B. Avinash
  • Patent number: 6206093
    Abstract: A system allows the pumping of viscous fluids from a wellbore. The system includes a submergible pump and a pump intake through which a fluid may be drawn. A submergible electric motor powers the submergible pump, and a heater is connected in the pumping system to heat the wellbore fluid. Additionally, a combination of heaters may be employed to heat the desired production fluid both externally to the pumping system and internally to the pumping system.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: March 27, 2001
    Assignee: Camco International Inc.
    Inventors: Woon Yung Lee, Diego Narvaez, Ketankumar K. Sheth, William B. Newberry
  • Patent number: 6206097
    Abstract: A pumping assembly for use on an offshore drilling platform. The pumping assembly includes a vertical pump designed for mounting on the deck of an offshore drilling platform. The pump is a vertical pump that includes a fluid intake, a fluid discharge, a rotatable shaft, and a fluid driving mechanism to draw fluid into the fluid intake and to discharge fluid through the fluid discharge. A seal is mounted about the rotatable shaft to prevent leaking of the pumped fluid along the rotatable shaft. Additionally, a power source is coupled to the rotatable shaft to power the vertical pump. The fluid discharge is oriented to discharge fluid in a direction generally axially aligned with the rotatable axis to limit transverse forces on the seal.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 27, 2001
    Assignee: Camco International, Inc.
    Inventor: Richard A. Stephens
  • Patent number: 6200906
    Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: March 13, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Christophe Pierrat
  • Patent number: 6201327
    Abstract: A motor protector for use in protecting an electric motor in a subterranean environment. The motor protector utilizes a dual chamber system for absorbing the expansion and contraction of the internal fluids of a submergible electric motor. One of the chambers provides for the expansion and contraction of the internal fluids of a submergible electric motor. The other chamber is in fluid communication with the subterranean environment. A gas pocket is disposed within the motor protector between and in fluid communication with both of the dual chambers. The volume of gas couples the fluid pressure of the subterranean environment to the internal fluids of the electric motor without direct contact between the internal fluids of the electric motor and fluids from the subterranean environment.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: March 13, 2001
    Assignee: Camco International, Inc.
    Inventor: Olegario Rivas
  • Patent number: 6198262
    Abstract: A circuit and method for controlling current drawn from two different voltage sources while maintaining regulation of a fixed output voltage during controlled switching of different sleep states required by the microprocessor and system board.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: March 6, 2001
    Assignee: Compaq Computer Corporation
    Inventors: George F. Squibb, Mark R. Trace
  • Patent number: 6197279
    Abstract: The present invention provides a method of delivering an emulsion or suspension containing a supersaturated gas into a gas-depleted environment. The method generally comprises the steps of preparing an emulsion or suspension, exposing the emulsion or suspension to a gas at a pressure greater than 2 bar, and delivering the emulsion or suspension to a gas-depleted environment at ambient pressure.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: March 6, 2001
    Assignee: Wayne State University
    Inventor: J. Richard Spears
  • Patent number: 6194305
    Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: February 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 6189582
    Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: February 20, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Alan R. Reinberg, Russell C. Zahorik
  • Patent number: 6190050
    Abstract: A wear-resistant bearing system utilizes a grid pattern of wear-resistant material. In instances where two bearing surfaces slide with respect to one another, such as with a thrust bearing, wear-resistant material strips are inlaid in the surrounding support material. The strips of wear-resistant material are arranged on each component such that the strips intersect one another when one component is moved with respect to the other. This transverse relationship or grid pattern promotes extremely long component life.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: February 20, 2001
    Assignee: Camco International, Inc.
    Inventor: Steven Campbell