Abstract: A delay is introduced into the output path of a synchronous device in response to a rising supply voltage. Specifically, as its supply voltage rises, a synchronous memory device may operate too quickly, particularly data output. To slow the rate at which the memory device outputs data, the clock which controls the data output rate is delayed by an amount correlative to the magnitude of the supply voltage.
Abstract: A packaged semiconductor device, such as a lead frame device, includes a circuit supported within an enclosure. The circuit is coupled to a plurality of conductive leads within the enclosure. The leads extend from the enclosure for electrically coupling the circuit to external circuitry. At least one of the leads is shielded to reduce inductive coupling and crosstalk between the leads during high frequency switching. The shielded lead has a conductive base, a non-conductive layer disposed on the base, and a conductive layer disposed on the non-conductive layer. The non-conductive and conductive layers may be formed prior to electrically coupling the lead to the circuit, or following assembly of the lead frame package. The shielding may extend into the package enclosure, or may terminate external to the enclosure.
Abstract: The present invention includes a guidewire device capable of delivering perfusion fluids to a vascular site while at the same time exhibiting handling characteristics associated with existing non-perfusion guidewires. Preferred embodiments include a perfusion guidewire which closely matches the dimensions and physical characteristics of standard guidewires. Preferred embodiments also permit high pressure perfusion of supersaturated solutions, and include a liquid flow path which will not promote bubble generation or growth, or destabilize a supersaturated solution.
Type:
Grant
Filed:
August 21, 1998
Date of Patent:
November 2, 1999
Assignees:
Wayne State University, TherOx, Inc.
Inventors:
J. Richard Spears, Philip S. Levin, Paul J. Zalesky
Abstract: An internal combustion engine having a combustion chamber divided into two regions by an arcuate barrier on the top of the piston and a complementary arcuate barrier formed in a cavity of the cylinder head. When the piston is at top dead center, the combustion chamber is effectively divided into two portions with approximately ten percent of the chamber being in the vicinity of a fuel injector and a spark plug. By this structure, the engine minimizes the amount of fuel used at idle and at very low power levels, and yet engine performance at higher power levels is not affected.
Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.
Type:
Grant
Filed:
October 30, 1997
Date of Patent:
October 19, 1999
Assignee:
Micron Technology, Inc.
Inventors:
Graham R. Wolstenholme, Fernando Gonzalez, Russell C. Zahorik
Abstract: A rotary drill bit for use in drilling holes in subsurface formations comprises a bit body having a leading face and a gauge region, a number of blades formed on the leading face of the bit and extending outwardly away from the axis of the bit so as to define between the blades a number of fluid channels leading towards the gauge region, a number of cutting elements mounted side-by-side along each blade, and a number of nozzles in the bit body for supplying drilling fluid to the fluid channels for cleaning and cooling the cutting elements. In each of the fluid channels, adjacent the gauge region, is an opening into an enclosed passage which passes internally through the bit body to an outlet which, in use, communicates with the annulus between the drill string and the wall of the borehole being drilled. The gauge region of the drill bit comprises a substantially continuous bearing surface which extends around the whole of the gauge region.
Type:
Grant
Filed:
December 9, 1998
Date of Patent:
October 19, 1999
Assignee:
Camco International (UK) Limited
Inventors:
Douglas Caraway, John Hayward, Malcolm R. Taylor, Tom Scott Roberts, Steven Taylor, Graham Watson
Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant species is an ionic molecule that contains titanium and boron.
Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon "floaters," which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses chemical mechanical planarization to remove the layer of polysilicon and an overlying layer of photoresist from the upper surface of the substrate in which a container is formed. A wet etch selectively isolates a rim of the polysilicon within the container to recess the a rim, while the remainder of the polysilicon in the container is protected by the layer of photoresist.
Abstract: The present invention provides a method of delivering an emulsion or suspension containing a supersaturated gas into a gas-depleted environment. The method generally comprises the steps of preparing an emulsion or suspension, exposing the emulsion or suspension to a gas at a pressure greater than 2 bar, and delivering the emulsion or suspension to a gas-depleted environment at ambient pressure.
Abstract: Methods and related equipment for drilling a wellbore in subterranean formations whereby a drill bit is attached to one end of a first conduit string, such as a casing string which is not usually used for drilling, and advancing the first conduit string and the drill bit into the subterranean formation to extend an existing wellbore, cleanout the wellbore or create a new lateral wellbore. This advancement is stopped and steps are taken to create a longitudinal opening through the drill bit. Thereafter, a second conduit string is advanced through the opening in the drill bit and into the subterranean formation to further extend, cleanout or create the lateral wellbore.
Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.
Type:
Grant
Filed:
May 9, 1997
Date of Patent:
September 14, 1999
Assignee:
Micron Technology, Inc.
Inventors:
Alan R. Reinberg, Russell C. Zahorik, deceased
Abstract: An apparatus and method for preventing gimballing in the polishing of a semiconductor wafer held in an overhanging position with respect to a polishing pad. One embodiment includes a support apparatus for use with a device for polishing a semiconductor wafer, the device having a rotatable wafer carrier and a polishing pad attached to a rotatable platen, the wafer carrier being movable to place a semiconductor wafer held by the wafer carrier in a contacting and overhanging relationship with the polishing pad. The support apparatus includes a support to prevent gimballing of the wafer carrier when the wafer held by the wafer carrier is in the overhanging and contacting relationship with the polishing pad, the support having a low polishing surface to contact and support the semiconductor wafer.
Abstract: A photomask is disclosed in which buffer regions are created in between areas of phase transitions to prevent the formation of null intensity areas on semiconductor wafers fabricated using the photomask of the present embodiment. The buffer regions are first patterned with opaque regions, which act as etch masks for adjoining phase-shifting layers. Then the opaque regions are removed, and the buffer regions may be etched to create buffer regions of varying phase angles.
Abstract: The present invention provides a method and apparatus of fabricating photomasks. The photomasks may be fabricated from a photomask blank structure having multiple layers. Upon patterning of these multiple layers by standard photolithographic processes, a photomask is created which is capable of phase-shifting incident light by various degrees, which may be 0.degree., 60.degree., 120.degree., and 180.degree..
Abstract: A method for fabricating photomasks including forming a resist layer located over a substrate, and heating the substrate at a temperature greater than the glass transition temperature of the resist, such that the resist layer flows. In this manner, defects such as pinholes within the resist layer are reduced.
Abstract: A method for forming a sidewall aligned contact structure without a hardmask layer. A semiconductor region is provided having an active area at an upper surface. An insulating layer is formed having an upper surface over the active area. Using a photo-patterned organic mask, a gross contact opening is etched in the insulating layer over the active area. The gross contact opening extends downward from the upper surface and partially through the insulating layer. A conformal layer of material is deposited at low temperature over the patterned mask as well as sidewalls and a bottom surface of the gross contact opening The conformal layer comprises a material that is differentially etchable with respect to the photomask and preferably etches similarly to the insulating layer. A portion of the insulating layer at the base of the gross contact opening is exposed. A contact opining is formed in the exposed portion of the insulating layer using the remaining conformal layer as a mask.
Type:
Grant
Filed:
February 6, 1997
Date of Patent:
August 3, 1999
Assignee:
Micron Technology, Inc.
Inventors:
Phillip G. Wald, Mark Fischer, William A. Stanton
Abstract: The present invention provides a method of delivering an emulsion or suspension containing a supersaturated gas into a gas-depleted environment. The method generally comprises the steps of preparing an emulsion or suspension, exposing the emulsion or suspension to a gas at a pressure greater than 2 bar, and delivering the emulsion or suspension to a gas-depleted environment at ambient pressure.
Abstract: A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.
Abstract: A multichip module includes a printed circuit printed circuit board onto which traces of electrically conductive material are formed and into which groups of plated vias are formed. Each group of vias is associated with an integrated circuit to be mounted in the assembly and has a spacing pattern that is identical to the spacing pattern of the bond pads of the integrated circuit with which it is associated. A layer of insulative adhesive material is provided, one side of which is attached to the printed circuit board. A plurality of integrated circuits are attached to the other side of the adhesive material. Each of the integrated circuits has a plurality of bond pads in a spacing pattern. A conductive contact is disposed in each via to connect a bond pad to that via.
Abstract: A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed circuit board (electrical only) as we now know it in the conventional SIMM module.