Patents Represented by Attorney Fletcher Yoder
  • Patent number: 6988074
    Abstract: A technique is disclosed for providing programs, such as operational protocols, to medical diagnostic institutions and systems. The protocols are created and stored on machine readable media. A description of the protocols is displayed at the diagnostic institution or system. A user may select a desired protocol or program from a user interface, such as a listing of protocols. The protocol listing may include textual and exemplary image descriptions of the protocols. Selected protocols are transferred from the machine readable media to the diagnostic institution or system. The transfer may take place over a network link, and may be subject to fee arrangements, subscription status verifications, and so forth. Protocols may be loaded for execution on system scanners by selection from the same or a similar protocol listing screen.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: January 17, 2006
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Ianne Mae Howards Koritzinsky, John Aurthur Reich
  • Patent number: 6987244
    Abstract: A welding system having a welding implement with a self-contained trigger and trigger locking assembly. The self-contained trigger and trigger locking assembly has a trigger which, when operated, regulates the flow of current from a power source. The trigger lock of the assembly has a movable portion which includes a groove which can engage a complementary structure on the trigger to maintain the trigger in an operating position, thereby allowing continued flow of current from the power source.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 17, 2006
    Assignee: Illinois Tool Works Inc.
    Inventor: Gregory W. Bauer
  • Patent number: 6984789
    Abstract: A method of making an electrical cable, the method comprising: bonding a plurality of electrical conductors to respective neighboring ones of the electrical conductors to form a ribbon, the electrical conductors being electrically insulated from the respective neighboring ones; folding the ribbon to form cable assembly, each of the electrical conductors traversing the width of the cable assembly at least twice; optionally bonding the cable assembly; and optionally coiling the cable assembly.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: January 10, 2006
    Assignee: General Electric Company
    Inventors: John Stanley Glaser, Judson Sloan Marte, Canan Uslu Hardwicke, Michael Andrew De Rooij
  • Patent number: 6983536
    Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren Farnworth, Alan Wood
  • Patent number: 6984894
    Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 6982552
    Abstract: Methods and apparatus for fabricating a magnetic resonance imaging (MRI) gradient coil for generating magnetic field gradients are provided. The method includes determining a pattern of gradient current paths on a surface using a set of stream functions oriented in at least one of a z-gradient, a y-gradient; and an x-gradient, and arranging conductive material to define a current path that conforms to the determined gradient current paths.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: January 3, 2006
    Assignee: General Electric Company
    Inventors: Christopher Judson Hardy, John Frederick Schenck, William Daniel Barber, Cornelius Jan Von Morze
  • Patent number: 6982176
    Abstract: A method for monitoring the quality of a manufacturing process for making detector panels that have a plurality of pixels in a two-dimensional array includes, in each detector panel, manufacturing a set of baseline pixels and a set of test pixels. Each test pixel has an electrical component having a geometric dimension varied by an amount sufficient to introduce a measurable variation in a test that measures parameters of pixels that are dependent upon the varied dimension. The method further includes performing the test on the set of baseline pixels and the set of varied pixels, analyzing the results of the test, and adjusting parameters of the manufacturing process in accordance with the analysis.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: January 3, 2006
    Assignee: General Electric Company
    Inventors: Aaron Judy Couture, Douglas Albagli, George Edward Possin
  • Patent number: 6983404
    Abstract: Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: January 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Douglas J. Cutter, Adrian E. Ong, Fan Ho, Kurt D. Beigel, Brett M. Debenham, Dien Luong, Kim Pierce, Patrick J. Mullarkey
  • Patent number: 6980928
    Abstract: This disclosure describes a system and method for providing efficiency and cost analysis for a power generation unit. The system of this disclosure includes a current condition data acquisition logic that acquires a plurality of current condition variables for the power generation unit. A design constants acquisition logic acquires a plurality of design constants for the power generation unit; and an analysis logic calculates a operational efficiency of the power generation unit. The method provides efficiency and cost analysis for a power generation unit. The method includes the steps of acquiring a plurality of current condition variables for the power generation unit, and acquiring a plurality of design constants for said power generation unit. With the current condition variables and design constants, the method calculates an operational efficiency of the power generation unit.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: December 27, 2005
    Assignee: General Electric Company
    Inventors: Catherine Mary Graichen, James Patrick Quaile, William James Sumner
  • Patent number: 6979415
    Abstract: A method of making a luminescent nanomaterial having a plurality of nanoparticles. The luminescent nanomaterial includes at least one lanthanide group metal phosphate and at least one lanthanide series dopant, wherein each of the plurality of nanoparticles has a predetermined morphology. The luminescent nanomaterial has a high quantum efficiency and a high absorption value. The method yields a variety of morphologies and sizes of the plurality of nanoparticles. The particles size of the luminescent material varies from tens of nanometers to a few hundred of nanometers.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: December 27, 2005
    Assignee: General Electric Company
    Inventors: Kalaga Murali Krishna, Mohan Manoharan, Geetha Karavoor, Shweta Saraswat, Sergio Paulo Martins Loureiro
  • Patent number: 6980624
    Abstract: A technique is provided for non-uniform weighting in back-projection calculations in tomosythesis. The non-uniform weighting may include weighting based on a count map of the number of times pixels of individual slices are traversed by radiation in different projections. Weighting may also include non-uniform functions for contributions of features at different slice level to the sensed X-ray attenuation system response inconsistencies are accounted for by further weighting based upon projection maps which may be created in separate system calibration or configuration routines.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: December 27, 2005
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventors: Baojun Li, Bernhard Erich Hermann Claus, Gopal B. Avinash, Stephen W. Metz, Jiang Hsieh
  • Patent number: 6979799
    Abstract: A welding system having a welding gun. The welding gun is adapted with a trigger. The welding gun may have a lever to lock the trigger in a desired pivoted position. The lever may pivot the trigger as the lever is pivoted. The welding gun may have a trigger extension to enable a user to pivot the trigger by depressing the trigger extension. The trigger extension may be plastically deformed. The trigger extension may be removable. The trigger extension may be rotatable.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: December 27, 2005
    Assignee: Illinois Tool Works Inc.
    Inventor: Robert J. Centner
  • Patent number: 6979849
    Abstract: A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor and the CAM portion of the memory cell. Conductive plugs are coupled to each of the transistors and coupled directly to the lower cell plate of the capacitor.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: December 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Richard Lane
  • Patent number: 6979904
    Abstract: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: December 27, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Jerry M. Brooks
  • Patent number: 6979528
    Abstract: A method and apparatus for baking a film onto a substrate. A film, such as a layer of photoresist, is disposed on a first surface of a substrate while a second surface is exposed to a liquid bath. The liquid bath is maintained at a pre-selected temperature. Exposure of the substrate to the liquid bath allows the film on the opposite surface to bake. The liquid bath is then re-circulated to maintain a constant and uniform temperature gradient across the substrate.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: December 27, 2005
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 6974333
    Abstract: A high-density connection of multiple circuit boards having overlapping ends arranged in a stack. The metal traces on the stacked circuit boards are electrically connected by contact of the ends of the traces, which ends may be pads. The stacked circuit boards can be clamped, soldered or bonded together. Multiple circuit boards may be connected to a single circuit board. In one embodiment, double-sided circuit boards are stacked so that a first circuit board connects to a second circuit board through a third circuit board disposed intermediate the first and second circuit boards. The circuit boards may be flexible or rigid.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 13, 2005
    Assignee: General Electric Company
    Inventors: Douglas Glenn Wildes, Robert Stephen Lewandowski, Geir Ultveit Haugen
  • Patent number: 6973157
    Abstract: A method and computer readable medium for generating a reconstructed volumetric image from projection image data acquired from an imaging system is provided. The method comprises accessing a plurality of projection image data and generating one or more weight maps from the projection image data. The reconstructed volumetric images are then generated from the weight maps and at least one of the plurality of projection image data and a plurality of processed projection image data derived from the plurality of projection image data.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: December 6, 2005
    Assignee: General Electric Company
    Inventor: Bernhard Erich Hermann Claus
  • Patent number: 6973219
    Abstract: A technique for reducing noise in pixel images includes shrinking a first image and a second, related, image, and processing the first shrunken image with a novel segmentation-based filtering technique which utilizes image data from the second shrunken image to help identify structures within the image. After the structures are identified, the first shrunken image is differentially processed to reduce image noise. After processing, the first shrunken image is enlarged to the dimensions of the initial data, subsequently processed if necessary and the final image is displayed or analyzed. The resulting technique is versatile and provides greatly improved computational efficiency while maintaining image quality and robustness.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 6, 2005
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventor: Gopal B. Avinash
  • Patent number: 6972587
    Abstract: An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and magnitude to program a programmable element that normally isolates a secondary circuit, such as redundant circuitry, from the remainder of the circuits on the device. Once programmed, the redundant circuitry may take the place of failed circuitry, and thus repair the device.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: December 6, 2005
    Assignee: Micron Technology, Inc.
    Inventor: David A. Zimlich
  • Patent number: 6970590
    Abstract: Apparatus and a method for locating edges of a part for acceptance testing of the part. A white light source (12) illuminates the part which is mounted on a support (14) and rotated relative to the light source. Light reflected by the part creates an outline of the part along the edge thereof. The part is viewed by a camera (16) to obtain an image of the part including its edge. A processor (18) analyzes the image to locate the edge of the part in three dimensional space. Analysis of the image includes determining the number of pixels comprising the viewed image, at the edge thereof, as the part is rotated relative to the light source. The part has more than one edge, and each edge is located using the method. The locations of the edges of the part are now used in a co-ordinate system to locate other surface features of the part.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 29, 2005
    Assignee: General Electric Company
    Inventor: Kevin George Harding