Patents Represented by Law Firm Fliesler, Dubb & Meyer
  • Patent number: 6509898
    Abstract: A method for generating a tree structure representation of a generalized graph structure for display includes the more important links in the representation. Usage parameters are referenced in generating the tree structure from the generalized graph structure. Frequency, recency, spacing of accesses, and path information are exemplary types of usage parameters. A breadth-first or depth-first traversal of the graph references usage parameters associated with each node or link. The usage parameters which are associated with each node are referenced in order to determine the visitation order. The visitation order is determined by visiting the highest used nodes or links first. A method of displaying the tree structure references the usage parameters to determine the positioning of the nodes in the layout of the tree structure. In a preferred embodiment, the root node is positioned in the center of the layout. In one example, sibling nodes are spread out on links which emanate radially about their parent.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: January 21, 2003
    Assignee: Xerox Corporation
    Inventors: Ed H. Chi, Peter L. T. Pirolli, James E. Pitkow, Rich Gossweller, Jock D. Mackinlay, Stuart K. Card
  • Patent number: 6509821
    Abstract: A microwave inductor including a coil with windings tapered from a first end of the coil to a second end of the coil to reduce resonant loss glitches found in conventional inductors which have uniform diameter windings. The coil further includes a core composed of a dielectric material containing a colloidal suspension of magnetic particles, the magnetic material preferably being iron powder and the dielectric preferably being epoxy, making the core a poly-iron material. The magnetic particles being colloidally suspended in dielectric increase the impedance of the coil at high frequencies to reduce resonant glitches without lowering the low frequency Q of the inductor. As such, a single coil can be utilized both in a filter which requires a low impedance at low frequencies to create a high Q, and as a bias line which operates at frequencies well beyond the resonant frequency of the inductor since a high impedance is provided by the core at higher resonant frequencies.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: January 21, 2003
    Assignee: Anritsu Company
    Inventor: William W. Oldfield
  • Patent number: 6507773
    Abstract: A robot which incorporates a body, two arms, two legs, several sensors, an audio system, a light assembly, and a video device. The sensors located throughout the body of the robot combined with an edge detection sensor allows the robot to interact with objects in the room, and prevents the robot from traveling off an edge or bumping into obstacles. The audio system allows the robot to detect and transmit sounds. The video device allows a user to remotely view the area in front of the robot. Additionally, the robot may operate in a plurality of modes which allow the robot to operate autonomously. The robot may operate autonomously in an automatic mode, a security mode, a greet mode, and a monitor mode. Further, the robot can be manipulated remotely.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: January 14, 2003
    Assignee: Sharper Image Corporation
    Inventors: Andrew J. Parker, Edward C. McKinney, Jr., Tristan M. Christianson, Richard J. Thalheimer, Shek Fai Lau, Mark Duncan, Charles E. Taylor
  • Patent number: 6504541
    Abstract: A system is disclosed for warping models made from geometric objects, such as electronic maps, to correct local distortions in the models without compromising model topology. A set of transformation functions are derived from relationships between points in a first model that match points in a second model. The transformation functions are then applied to the points in the first model to generate a new model with reduced distortion. In order to provide for reducing local distortions, warping is applied to selected corresponding regions of the first model and the second model by triangulating these regions and generating transformation functions for each corresponding pair of triangles. Topology preservation is achieved by identifying matching points in the first model and the second model that have a potential for causing topology deviations. Such matching points are then excluded from the process of developing transformation equations to be used in the warping process.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: January 7, 2003
    Assignee: Tele Atlas North America, Inc.
    Inventors: Hongche Liu, Shyam Kuttikkad
  • Patent number: 6504547
    Abstract: A method for implementing a bitmapped graphics system involves creating a logical frame buffer for a program. The method attaches a standardization operation to the logical frame buffer, so that the standardization operation is automatically executed upon the invocation of draw function by an application. The standardization operation serves to perform all of the functions required to properly transmit the contents of the logical frame buffer into the hardware frame buffer, arbitrates access to the logical frame buffer, if necessary, and performs other useful logical operations. In the preferred embodiment, the standardization operation comprises a complementary pre-process and a post-process. The pre-process is invoked prior to the execution of a graphics system draw operation, while the post-process is invoked thereafter. The pre-process and post-process may include more than one distinct pre-function and post-function.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: January 7, 2003
    Assignee: Pixo, Inc.
    Inventor: Paul Mercer
  • Patent number: 6504449
    Abstract: A phase compensated switched attenuation device 6 is provided for attenuating high frequency signals while maintaining an insertion loss of less than 1 dB up to 3 GHz. A single GaAs FET 12 is coupled between input port 8 and output port 9 in parallel with a 20 dB pad 10 for switching the device 6 between a through state and an attenuation state. First and second isolation FETs 14 and 16 are coupled between the GaAs FET 12 and pad terminals 18 and 19 to isolate the GaAs FET 12, decrease return loss when the GaAs FET 12 is on, and increase isolation of the GaAs FET 12 from the pad 10 when the GaAs FET 12 is on. A resistor 24 or a series combination of a resistor 24 and capacitor 26 can be coupled to the pad terminals 18 and 19 in parallel with the pad 10 to improve return loss when the GaAs FET 12 is on. Resistors 21, 22, and 23 are also provided to reduce distortion, coupling gates of the FETs 12, 14, and 16 to a plurality of voltage references V1 and V2.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: January 7, 2003
    Assignee: Anritsu Company
    Inventors: Cornelius Constantine, Richard G. Barber
  • Patent number: 6500314
    Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: December 31, 2002
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
  • Patent number: 6501317
    Abstract: A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors 104,106 and 105, 107 provide loads for the differential transistor 102 and 103. Transistors 111-114 and 121-122 together with an amplifier 130 provide biasing for the delay device. The amplifier 130 has a non-inverting input set to VDD−VCLAMP. As configured, a constant output voltage swing from VDD to VDD−VCLAMP is provided at the outputs VOUT+ and VOUT− of the delay device, independent of a control voltage VCTL used to set the tail current. The NMOS load transistor 104, as opposed to the PMOS transistor 4 in FIG. 1, does not contribute to the gate parasitic capacitance enabling a high operation speed without consumption of more supply current.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: December 31, 2002
    Assignee: Elantec Semiconductor, Inc.
    Inventors: Xijian Lin, Barry Harvey, Alexander Fairgrieve
  • Patent number: 6501681
    Abstract: An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer after a typical erase operation to be detected effectively with a high degree of sensitivity.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: December 31, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Van Buskirk, Narbeh Derhacobian
  • Patent number: 6500178
    Abstract: A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: December 31, 2002
    Assignee: St. Francis Medical Technologies, Inc.
    Inventors: James F. Zucherman, Ken Y. Hsu, T. Wade Fallin, Henry A. Klyce
  • Patent number: 6499034
    Abstract: A method and computer readable medium for generating a graph which displays amounts of access to computer files, such as URL's on the world wide web, over a period of time. Time is mapped along a central axis, and a plurality of file identifiers is mapped radially about the radial axis as lines having varying distances from the radial axis. The lines may be arranged at angles of rotation about the radial axis and are colored to represent the lexicographical similarity of the nodes. Alpha bending is utilized to reveal lines having an angle of rotations near 0 degrees that would otherwise be concealed by neighboring lines. In an alternative embodiment, a two dimensional graph displays instantaneous access information for a plurality of file identifiers, where angular rotation and color may also be used to represent the grouping of the nodes, and distances of radial lines from an origin represent access values to respective files.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: December 24, 2002
    Assignee: Xerox Corporation
    Inventor: Jock D. Mackinlay
  • Patent number: 6498601
    Abstract: A palmtop computer for entering characters using one or more input modes. In one example, a physical sensor is coupled to select the input mode. The physical sensor may be in the form of a button, rocker switch, dial, pressure strip, moveable bar, or accelerometer mounted to the device. The physical sensor may also be mounted to a pen. In another example, a ridge is formed on the digitizer pad and positioned to define input regions associated with particular input mode. In another example, a border is formed around the digitizer pad. The border includes a ridge coupled to select the input mode. The digitizer pad may also be textured. A first textured region is associated with one input mode and a second textured region is associated with another input mode.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: December 24, 2002
    Assignee: Xerox Corporation
    Inventors: Anuj Uday Gujar, David Goldberg, Kenneth P. Fishkin, Beverly L. Harrison, Roy Want
  • Patent number: 6498361
    Abstract: On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: December 24, 2002
    Assignee: Lightspeed Semiconductor Corporation
    Inventor: Robert Osann, Jr.
  • Patent number: D467275
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 17, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D467277
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: December 17, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D467278
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: December 17, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D467612
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 24, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D467967
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: December 31, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D467968
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: December 31, 2002
    Inventor: Joel B. Shamitoff
  • Patent number: D468353
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: January 7, 2003
    Inventor: Joel B. Shamitoff