Abstract: A semiconductor device, full bridge converter employing the same, and methods of fabrication thereof are provided. The device includes a vertical MOSFET having a parasitic body diode at a junction face between a body region and a semiconductor layer thereof. The parasitic body diode is suppressed by having no direct electrical connection to the body region, resulting in the parasitic body diode being open-circuited within the MOSFET. Co-packaged with the MOSFET is a separate bypass diode connected across a source and a drain of the MOSFET. The bypass diode functions to clamp the voltage across the MOSFET without employing the parasitic, electrically isolated body diode of the MOSFET.

Abstract: A method of use and apparatus for a quick connect coupling in a fluid system as disclosed herein. The quick connect coupling includes a female coupling assembly and a male coupling assembly. The female coupling assembly includes a female cone housing nestable with a female cone. At least one female flow hole is formed in each of the female cone housing and female cone. The male coupling assembly has a male cone housing nestable with a male cone. At least one male flow hole is formed in each of the male cone housing, and the male cone. The at least one female flow hole rotatably misaligns to seal in a manner that fluid is contained from leaking past the female coupling assembly. The at least one male flow hole rotatably misaligns to seal in a manner that fluid is contained from leaking past the male coupling assembly. The male coupling assembly is removably rotatably insertable into the female cone.

Abstract: The present invention provides fiber channel networks the ability to use extended link service commands to convey implementation dependent information between ports.

Abstract: An exemplary embodiment of the present invention is a system having a diverse hardware platform monitored and managed from a central control node in a distributed, parallel, heterogeneous computing environment. The central control node executes both a hardware monitor program and an intermediary program to monitor and manage diverse hardware in a distributed, parallel, heterogeneous computing environment. The intermediary program emulates network frame hardware by facilitating communication between the hardware monitor program and diverse node hardware. Another exemplazy embodiment of the present invention is a method for facilitating communication between a hardware monitor for monitoring and management of node hardware and for providing an interface for administrator interaction with the node hardware and diverse node hardware in a distributed, parallel, heterogeneous computing environment.

Abstract: An exemplary embodiment is a method and apparatus for planarization. The planarization tool has a base which provides the support for the planarization tool. The base has a support hinge mounted on it along with dampening posts and rest posts which support a pivot plate hinged to the support hinge. A pressure assembly is mounted to the pivot plate by retention hardware. The pressure assembly loads a device under test board assembly that is mounted to the pressure assembly with the retention hardware.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which participated in a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: A physical clock is expanded to enhance its precision. Existing instructions are capable of using the enhanced physical clock. Execution of an instruction begins, which places a value of the expanded physical clock in a physical clock field of a clock representation. The physical clock field is, however, unable to accommodate the value provided by the expanded physical clock. Thus, that value encroaches upon another predefined field of the clock representation. Completion of the instruction is therefore delayed such that the value provided by the expanded physical clock can be accommodated in the clock representation and a correct value for the another predefined field can be provided.

Abstract: A multicasting apparatus that broadcasts messages to at least some of the clients in a computing network environment having a plurality of clients and at least one host connected to these clients via a gateway device. A multicast routing table is created for registering any host and clients requesting registration. The table will include one entry per host/client and includes their relevant information. A connectivity platform is used for controlling all communications so that all information packets is first received by the platform. Upon the receipt of a packet, the table is searched and if an match is found the packet will be routed using the entry information; otherwise, the packet will be dropped.

Abstract: Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds notwithstanding unavailability of at least one processor of the quorum group of processors assuming that a quorum of the remaining processors exists. Recovery processing is implementing by the group of processors so that the at least one processor which was unavailable during the dynamic reconfiguration of the group is able to obtain current state information once becoming active. Each processor of the group of processors includes an incarnation number and a list of member processors which resulted from a commit process resulting in its incarnation number. The recovery processing includes exchanging the processors' incarnation numbers and lists of processors for propagation of the current state of the quorum group of processors to the at least one processor now becoming available.

Abstract: A management facility for managing concurrently executable computer processes. The management facility includes a registration mechanism, which enables a plurality of interdependent processes to be considered a part of a topology of logically dependent execution groups, and a termination synchronization mechanism that synchronizes the completion of termination for the processes within the topology. Termination synchronization prevents a process within the topology from completely terminating, even if it has entered normal termination, until all of the processes within the topology have normally terminated. If one of the processes within the topology has abnormally terminated, then notification of this abnormal termination can be propagated to all of the processes within the topology of logically dependent execution groups, since none of them have completely terminated.

Abstract: An exemplary embodiment of the invention is an actuation system including a printed circuit board having a plurality of interconnects and a compression connector positioned adjacent the printed circuit board and having a plurality of contacts for engaging the interconnects. A processing module is positioned adjacent the compression connector. The processing module has a base and a plurality of terminals for engaging contacts on the compression connector. An actuator includes a fastener that engages the base of the processing module and a biasing member for maintaining a force on the compression connector.

Abstract: A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages.

Abstract: The present invention provides for a method of transferring information in a network computing system environment. The network environment includes a main storage coupled to a channel subsystem with a plurality of channels which is in processing communication with a control unit capable of coupling to a plurality of input/output devices. At first the packets of data are sent concurrently to and from the main storage. Next execution of certain channel functions are transferred to the control unit so that certain commands can be combined with the data packets in one sequence. Finally only one start data command and only one end command notification needs to be sent before and after a plurality of data packets is transferred respectively.

Abstract: A fractal process scheduler for testing applications in a distributed processing system having a plurality of nodes. The scheduler includes an originating file containing a sequence of statements, each statement representing a fractal cell, an input file comprising statements from said originating file which generate vertices, a fractal parser for compiling the statements from the input file, one or more intermediate files produced by the fractal parser comprising intermediate results. The intermediate files are executable for scheduling a process of the application being tested to nodes of the distributed processing system. The schedular further includes a master file produced by said fractal parser, said master file which is executable for scheduling a process of the application being tested to nodes of the distributed processing system. The fractal parser maps the input file into the intermediate file and the master file in accordance with complex fractal expansions.

Abstract: A program product recorded on a computer readable medium in which the program product includes a method of performing a software operation on a target of one or more processors in a distributed processing system wherein another processor is designated as a server.

Abstract: A method and apparatus for detection of a bus hang with identification and capturing of errors in a network computing environment having at least one bus. A first and a second unit are in processing communication with one another in the environment and both units are capable of transferring data between one another. A status circuit is provided for monitoring the first and second units as well as a counting circuit that is measuring periods of bus inactivity during an active bus transfer sequences. A compare circuit is in processing communication with the first and second units for comparing threshold counts provided with a threshold value circuit. Finally, an error detector mechanism that is responsive to the threshold circuit is provided, capable of detecting a bus hang condition, where the detector asserts an error indication when appropriate.

Abstract: A refrigeration system includes an evaporator housing sealed to a first side of a circuit board containing a logic module, the evaporator housing including an evaporator block in thermal communication with the logic module. The evaporator housing further includes at least a humidity sensor for detecting a humidity within the evaporator housing. In another aspect of the invention, the refrigeration system includes a heater on a second side of the circuit board opposite the evaporator housing, the heater being in thermal communication with plated through-holes of the circuit board to maintain the circuit board above local ambient temperature. In another aspect of the invention, a source of dry pressurized air is provided into the sealed evaporator housing through a though-hole drilled directly under the logic module.

Abstract: Controlling the flow of information between senders and receivers across links being used as channels. In one example, a self-timed interface link is adapted to be used as a channel. Such an interface is referred to as an integrated cluster bus. The flow control for the integrated cluster bus includes, for instance, a Data Request packet that indicates to the transmitter of data that it can now send the data; a continue indicator that specifies that more data is to follow; and a sequence indicator that is used to determine if a particular message is in proper sequence order. The integrated cluster bus does not require large data buffers and offers low latency messaging.

Abstract: An initialization facility is provided for a fiber optic data link wherein the link can be initialized in one of a plurality of fiber control modes, including one or more open fiber control (OFC) modes and a non-OFC mode. Initialization may be automatic, being responsive to received optical signals, or user determined. Along with the initialization facility, safety logic is presented which allows the facility to be fully compliant with industry standard laser safety requirements for inherently safe Class 1 operation. Further, logic is provided for controlling resetting of an OFC chip. In one embodiment, the facility can be implemented in an auto-sense circuit coupled between a conventional OFC chip and a transceiver of the fiber optic data link.

Abstract: A completely passive and self-contained solid-state circuit interrupter for removing DC power while mating and unmating connectors is integrated into a connector housing. An electronic mechanism is employed to de-energize the power contacts while the mating connectors are more than a predetermined distance apart.