Patents Represented by Attorney Fogg & Powers, LLC
  • Patent number: 8325522
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Patent number: 8327248
    Abstract: A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 4, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Harold William Satterfield, Grady M. Wood
  • Patent number: 8324538
    Abstract: Systems and methods to source a resistive load, such as a heating resistor, to control temperature while adhering to a specified power draw budget and/or a specified root mean square (RMS) current limit. For example, a sensor block assembly (SBA) heater controls temperature of a MEMS device in a sensor block assembly while adhering to the power draw budget and/or an average current limit. An exemplary embodiment generates a pulse width modulation (PWM) control signal, controls a switch in accordance with the control signal, sources the resistive load from a power source in accordance with the controlled switch, and modifies the duty factor of the switch to reduce the power drawn by the resistive load in response to the power drawn by the resistive load exceeding a power limit defined by a slope-intercept curve. The limiting of power into a resistor load limits the RMS current drawn by that load.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 4, 2012
    Assignee: Honeywell International Inc.
    Inventor: Paul Schwerman
  • Patent number: 8326359
    Abstract: A reconfigurable wireless modem adapter is provided. The reconfigurable wireless modem adapter includes a control board and a radio frequency switch. The control board has at least two interfaces for a respective at least two modems and is configured to communicatively couple to at least one onboard system in a vehicle. The control board activates a selected modem interfaced to one of the at least two interfaces. The radio frequency switch is communicatively coupled to the control board via the selected one of the at least one modem. The radio frequency switch communicatively couples an antenna to the selected modem. When the control board is communicatively coupled to the at least one onboard system and activates the selected modem, and when the radio frequency switch is communicatively coupled to the antenna, the antenna is communicatively coupled to the at least one onboard system via the selected modem.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: December 4, 2012
    Assignee: Honeywell International Inc.
    Inventor: Donald C. Kauffman
  • Patent number: 8326218
    Abstract: A digital radio frequency transport system that performs bi-directional simultaneous digital radio frequency distribution is provided. The transport system includes a digital host unit and at least two digital remote units coupled to the digital host unit. The bi-directional simultaneous digital radio frequency distribution is performed between the digital host unit and the at least two digital remote units.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 4, 2012
    Assignee: ADC Telecommunications, Inc.
    Inventor: Philip M. Wala
  • Patent number: 8316552
    Abstract: Systems and methods for three-axis sensor chip packages are provided. In one embodiment, a directional sensor package comprises: a base; a first sensor die mounted to the base, the first sensor die having a first active sensor circuit and a first plurality of metal pads electrically coupled to the first active sensor circuit; a second sensor die mounted to the base, the second sensor die having a second active sensor circuit located on a first surface, and a second plurality of metal pads electrically coupled to the second active sensor circuit located on a second surface. The second sensor die is positioned such that the second active sensor circuit is oriented orthogonally with respect to the first active sensor circuit region and is perpendicular to the base. The second surface is adjacent to the first surface and angled with respect to a plane of the first surface.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: November 27, 2012
    Assignee: Honeywell International Inc.
    Inventors: Lakshman Withanawasam, Ryan W. Rieger, Bharat B Pant
  • Patent number: 8320180
    Abstract: A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: November 27, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Alexander Kalnitsky, Michael D. Church
  • Patent number: 8316192
    Abstract: Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: November 20, 2012
    Assignee: Honeywell International Inc.
    Inventors: Scott Gray, Nicholas Wilt
  • Patent number: 8316368
    Abstract: One example is directed to a method of generating a set of schedules for use by a partitioning kernel to execute a plurality of partitions on a plurality of processor cores included in a multi-core processor unit. The method includes determining a duration to execute each of the plurality of partitions without interference and generating a candidate set of schedules using the respective duration for each of the plurality of partitions. The method further includes estimating how much interference occurs for each partition when the partitions are executed on the multi-core processor unit using the candidate set of schedules and generating a final set of schedules by, for at least one of the partitions, scaling the respective duration in order to account for the interference for that partition. The method further includes configuring the multi-core processor unit to use the final set of schedules to control the execution of the partitions using at least two of the cores.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: November 20, 2012
    Assignee: Honeywell International Inc.
    Inventors: Stephen C. Vestal, Pamela Binns, Aaron Larson, Murali Rangarajan, Ryan Roffelsen
  • Patent number: 8315100
    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 20, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Hosam Haggag, Alexander Kalnitsky, Edgardo Laber, Michael D. Church, Yun Yue
  • Patent number: 8315794
    Abstract: A method and system for navigation of one or more unmanned aerial vehicles in an urban environment is provided. The method comprises flying at least one Global Positioning System (GPS)-aided unmanned aerial vehicle at a first altitude over an urban environment, and flying at least one GPS-denied unmanned aerial vehicle at a second altitude over the urban environment that is lower than the first altitude. The unmanned aerial vehicles are in operative communication with each other so that images can be transmitted therebetween. A first set of images from the GPS-aided unmanned aerial vehicle is captured, and a second set of images from the GPS-denied unmanned aerial vehicle is also captured. Image features from the second set of images are then matched with corresponding image features from the first set of images. A current position of the GPS-denied unmanned aerial vehicle is calculated based on the matched image features from the first and second sets of images.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: November 20, 2012
    Assignee: Honeywell International Inc.
    Inventors: Dennis W. Strelow, Alan B. Touchberry
  • Patent number: 8315274
    Abstract: Apparatus and methods are provided for controlling synchronous and asynchronous communications in an avionic network. The method includes receiving one or more asynchronous messages and one or more synchronous messages, allocating each of the synchronous messages to a corresponding predetermined time slot while producing an unoccupied portion in at least one of the predetermined time slots, and allocating the asynchronous messages to one or more of the unoccupied portions of the predetermined time slots.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 20, 2012
    Assignee: Honeywell International Inc.
    Inventors: Dave Bibby, David A. Dietz, Brett A. Eddy
  • Patent number: 8315793
    Abstract: An integrated sensor device is provided. The integrated sensor device comprises a first substrate including a surface portion and a second substrate coupled to the surface portion of the first substrate in a stacked configuration, wherein a cavity is defined between the first substrate and the second substrate. The integrated sensor device also comprises one or more micro-electro-mechanical systems (MEMS) sensors located at least partially in the first substrate, wherein the MEMS sensor communicates with the cavity. The integrated sensor device further comprises one or more additional sensors.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 20, 2012
    Assignee: Honeywell International Inc.
    Inventor: Lakshman Withanawasam
  • Patent number: 8310963
    Abstract: A system comprises a first unit and a second unit communicatively coupled to the first unit. The first unit is operable to receive a first original radio frequency signal and the second unit is operable to receive a second original radio frequency signal. The first and second original radio frequency signals are originally transmitted on a radio frequency channel using time division duplexing. The first unit communicates a control signal to the second unit, the first unit generating the control signal based at least in part on detecting when the first original radio frequency signal is being received at the first unit. The second unit uses the control signal to determine when to output a first reproduced radio frequency signal in accordance with the time division duplexing used to originally transmit the first and second original radio frequency signals on the radio frequency channel. The first reproduced radio frequency signal is derived from the first original radio frequency signal.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 13, 2012
    Assignee: ADC Telecommunications, Inc.
    Inventor: Baljit Singh
  • Patent number: 8305070
    Abstract: A controller and methodology for a power supply are disclosed. The controller includes output channels for providing a pulse width modulation (PWM) voltage signal for driving a load, for example, a microprocessor. Each channel provides a portion of the PWM signal. The controller receives user input information and uses that information to automatically determine window sizes. A window size defines the maximum output current level for a given window. The controller uses feedback signals to determine the current being drawn by the load, and selects the number of windows and channels that are needed to adequately provide that current. The controller selectively activates and deactivates the output channels accordingly. In response a change in the user input information the controller automatically adjusts the window sizes.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: November 6, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Salomon Vulih, Timothy Maher, Douglas M Mattingly
  • Patent number: 8306153
    Abstract: Embodiments of the invention relate to systems and methods for tracking phase in a receiver which uses multiple phase tracking techniques. A phase tracking module generates a plurality of symbol decisions related to received 8-level-vestigial-sideband (“8VSB”) signals, determines a phase tracking threshold value based on a mean square error, receives an estimated imaginary component of a transmitted signal based on the symbol decisions, and determines a phase estimate based on the imaginary component of the transmitted signal and the plurality of symbol decisions. The phase tracking module selects one of a first phase tracking technique and a second phase tracking technique based on the phase estimate. The first phase tracking technique is selected when the phase estimate is greater than the phase tracking threshold value, and the second phase tracking technique is selected when the phase estimate is less than the phase tracking threshold value.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: November 6, 2012
    Assignee: Techwell LLC
    Inventor: Gregory J. Tomezak
  • Patent number: 8305067
    Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: November 6, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Chun Cheung, Weihong Qui, Robert Isham
  • Patent number: 8306676
    Abstract: Systems and methods for differential altitude estimation utilizing spatial interpolation of pressure sensor data are provided. In one embodiment, a method for mobile navigation comprises: measuring a horizontal location of a mobile navigation unit to generate two-dimensional horizontal coordinate data; measuring a barometric pressure at the mobile navigation unit with a sensor to obtain local pressure data; processing information representative of pressure data derived from a network of a plurality reference stations to obtain a correction factor; performing a calculation using the two-dimensional horizontal coordinate data, the local pressure data, and the correction factor to calculate an altitude coordinate; and determining an altitude of the mobile navigation unit from the altitude coordinate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: November 6, 2012
    Assignee: Honeywell International Inc.
    Inventors: Ryan Ingvalson, Michael R. Elgersma, Wayne A. Soehren
  • Patent number: 8305208
    Abstract: A method for prompting an operator to reply to a first data link message before it expires includes receiving the first data link message, storing the first data link message, starting a timer at an initial timer value when the first data link message is received, determining whether a response to the first data link message has been input, determining whether the timer will expire in less than a predefined amount of time, requesting an input from the operator before the timer expires, determining whether the input has been received since requesting input, and determining whether the timer has expired before the input is received. In cases where the input is received before the timer expires, a second data link message is sent. In cases where the input is not received before the timer expires, a status for the first data link message is set to expired.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 6, 2012
    Assignee: Honeywell International Inc.
    Inventor: Thomas D. Judd
  • Patent number: RE43808
    Abstract: A double-ended, DC-AC converter supplies AC power to a load, such as a cold cathode fluorescent lamp used to back-light a liquid crystal display. First and second converter stages generate respective first and second sinusoidal voltages having the same frequency and amplitude, but having a controlled phase difference therebetween. By employing a voltage controlled delay circuit to control the phase difference between the first and second sinusoidal voltages, the converter is able to vary the amplitude of the composite voltage differential produced across the opposite ends of the load. The converter may be either voltage fed or current fed.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: November 20, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Robert L. Lyle, Jr., Steven P. Laur, Zaki Moussaoui