Abstract: A modulation controller includes an error amplifier which receives a reference voltage and an output voltage (VOUT) from a switching regulator being controlled by the controller at its inputs and provides a VCOMP signal at its output, and at least one comparator, wherein a first input of the comparator is coupled to an output of the error amplifier and a second input coupled to receive a ramp signal. A VCOMP shift cancellation circuit is interposed between the first or second input of the comparator, wherein the VCOMP shift cancellation circuit improves diode conduction mode performance (DCM) of the regulator by reducing a variation in average VCOMP.

Abstract: A microelectromechanical system (MEMS) hermetically sealed package device that is less labor intensive to construct and thus less expensive to manufacture. An example package device includes a package having a bottom section and a lid. A MEMS die includes upper and lower plates made in accordance with upper sense plate design. The MEMS die is mounted to the bottom section. The upper and lower plates form a cavity that receives a MEMS device. The upper and lower plates are bonded by one or more bond pads and a seal ring that surrounds the cavity. The seal ring includes grooves that allow exposure of the cavity to the space within the package. A getter material applied to a top surface of the MEMS die on the upper plate. The getter material is activated during or after the lid is mounted to the bottom section.

Abstract: A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.

Abstract: A method to dynamically reconfigure a network by receiving a data packet for transmission from a node in the network at a media access control layer of the node and determining a slot assignment for the data packet based on an application required quality of service. The application required quality of service is determined based on at least one of a number of slots required by the data packet, an application-specified data rate, an application-specified delay requirement and an application-specified number of reserved retries, and application-associated priority values for the data packet. The media access control layer is enabled for time division multiple access.

Abstract: A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (VOUT) of the converter, wherein a load current flows through the inductor. VOUT is fed back through a network including a feedback resistor (RFB) to an inverting input of the error amplifier. A circuit for sensing the load current includes a first operational amplifier, a sense resistor on the chip having resistance RSENSE coupled to an inverting input of the first amplifier; wherein a sense current related to the load current flows through the sense resistor, a dependent current source provides an output current to supply the sense current. A reference resistor is disposed on the chip having a resistance RREFERENCE which is a fixed multiple of RSENSE. A set resistor is provided having a resistance RSET.

Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

Abstract: A method of upgrading the system capability of a communications network is provided. The method involves initiating a transfer of at least one set of upgraded system capability software machine-coded instructions to a host card, instructing the host card to begin an upgrade process, determining whether at least one set of system capability software machine-coded instructions on the host card is valid, and completing the transfer of at least one valid set of system capability software machine-coded instructions to the host card, wherein the system capability is upgraded without affecting operation of the network.

Abstract: A pole mount bracket is provided. The bracket includes at least one extruded portion, a pole mounting portion and a band. The at least one extruded portion has an engaging surface. The engaging surface has a plurality of grooves that allow the extruded portion to bend to the form of a pole. The pole mounting portion is connected to the at least one extruded portion. Moreover, the pole mounting portion is further configured to be selectively coupled to a device. The band is configured to deform the at least one extruded portion about the pole to attach the pole mount bracket to the pole.

Abstract: A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Abstract: A method and system for increasing the precision of time synchronization among a plurality of host nodes in a packet-switched network by reducing transmission delay variation in the network. Each host node is provided with a distinct set of transmission times selected from a global schedule in such a way as to avoid concurrent transmission of messages by the plurality of host nodes. The transmission times may be determined as offsets within a global hyperperiod, and each host node carries out transmissions according to predetermine offsets the respective host node. Transmissions according to offsets may be applied to real-time messages, including time-synchronization messages, hence yielding increase precision of synchronization.

Abstract: A scalable network is provided. The network includes a remote device coupled to an antenna and adapted to communicate with subscriber units over an RF link, a switching device coupled to the remote device, and a radio suite coupled to the switching device. The radio suite includes two or more radios, each radio performs the functions of a base station transceiver. The switching device interconnects the radio suite with the remote device. Each radio supports one or more air interface standards.

Abstract: Method and apparatus for situation-based management of natural and artificial systems using event correlation and a situation manager. Input is provided from multiple sources in the form of a collection of events. A first level of processing performs event correlation over the collection of events and infers new events and new qualities of events. A second level of processing manages situations based on the collection of events, where situations are recognized, maintained, and given a degree of confidence. Situations are periodically updated based on incoming events. The assertion of a situation may call for information from external sources, provide information for external sources, and provide control instructions to external sources. Given a current situation, past, and possible future situations are inferred. Additionally, a method and apparatus for bi-directional communication between the event correlator and situation manager.

Abstract: A static partition scheduling timeline is generated by identifying a plurality of partitions for scheduling, the partitions associated with a operating system that executes on a processing unit. A first plurality of Activation Frames for a first partition of said plurality of partitions is defined, a second plurality of Activation Frames for a second partition of said plurality of partitions is defined, a first plurality of slices within at least one Activation Frame of said first plurality of Activation Frames is defined, and a second plurality of slices within at least one Activation Frame of said second plurality of Activation Frames is defined. The static partition scheduling timeline comprises the first plurality of Activation Frames, the second plurality of Activation Frames, the first plurality of slices, and the second plurality of slices. The operating system is configured to use the generated static partition scheduling timeline.

Abstract: A network comprises a plurality of nodes; a plurality of bi-directional point-to-point communication links, wherein a priority-based arbitration scheme is used to communicate over each of the plurality of point-to-point links; and a hub that is communicatively coupled to each of the plurality of nodes via the plurality of point-to-point links; wherein when the hub determines that one or more of the nodes is transmitting a message via the hub, the hub selects which node's message should be forwarded to the other nodes based, at least in part, on the priority-based arbitration scheme and forwards the selected node's message to the other nodes with elevated priority.

Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

Abstract: In one embodiment, a node comprises an interface to communicatively couple the node to a plurality of independent communication links. The node changes the mode in which the node operates when the node receives an indicator on a plurality of the independent communication links.

Abstract: A navigation system having a radar altimeter is disclosed. The navigation system comprises a signal processing unit and one or more antennas in operative communication with the radar altimeter and the signal processing unit. The system further comprises a forward looking radar communicatively coupled to the radar altimeter. The forward looking radar and the signal processing unit are configured to provide forward looking radar measurements, radar altitude measurements from the radar altimeter, and datalink communications within a single forward looking radar scanning sequence.

Abstract: A memory system that disperses memory addresses of strings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store strings of data. The CPU is configured to direct the storing and retrieving of the strings of data from the memory at select memory addresses. The address randomizer is coupled between the CPU and the memory. Moreover, the address randomizer is configured to disburse the strings of data throughout locations of the memory by changing the select memory addresses directed by the CPU.

Abstract: A user-programmable bi-directional, constant current generator circuit allows external programming of either a positive (+) or a negative (?) polarity output current, for injection into one of two locations of the PWM controller circuit of a DC-DC voltage converter. The parameters of the DC-DC converter's offset voltage will depend upon the connection of a single programming pin to one of two programming resistors. The programming resistors are respectively referenced to different supply rail voltages (VCC and VSS). The polarity of the offset additionally depends upon where, within the PWM-controlled DC-DC converter, the programmed constant current is injected.