Abstract: A method for controlling a plurality of service units in a telecommunications system with a multi-carrier transmission scheme is provided. Specifically, in one embodiment, the method includes broadcasting control signals for the service units over a plurality of control channels distributed in a number of subbands of a frequency bandwidth. The method further includes identifying the service unit to use the control signal with an identifier.

Abstract: A scanning method for establishing communication between a head end and a plurality of remote units in a multi-point to point communication system is described. The method includes transmitting information from the head end to the plurality of remote units in a plurality of regions of a first frequency bandwidth, each of the regions having at least one control channel associated therewith, identification information corresponding to each of the remote units of the plurality of remote units being periodically transmitted from the head end on the at least one control channel of one of the plurality of regions of the first frequency bandwidth.

Abstract: A memory device has a segmented memory cell array that take a row address and a column address and allows for data words in a column page to be read internally in parallel for faster access. The memory device employs a segmented memory array that routes column address and column address+1 to the segments. This allows for a random starting data word in the column page, while the data words in the next column page (column address+1) are loaded into the memory array segments before the starting data word. When the data page mode or linear burst access crosses a column address boundary the next data words in column address+1 are available and no wait states need to be asserted to allow for new column address values to propagate.

Abstract: A flash memory device incorporating redundant rows. The memory device includes a memory array, control circuitry and a register. The control circuitry controls operations to the memory array. The register stores an address of a defect in the memory array and data indicating a type of defect associated with the address. The control circuitry increments row addresses during an erase operation based on the type of defect stored in the register.

Abstract: A method of transmitting data in a communication system is provided. The method includes adjusting upstream power levels in a multipoint-to-point communications system having a head end and a plurality of service units is provided. The method includes measuring power levels of signals from the service units at the head end and comparing the power levels with a nominal power level. Further, the method provides at least one coarse adjustment at the service units to correct for large variations between the measured power level nominal power level and at least one fine adjustment at the head end to correct for smaller variations between the measured power level and the nominal power level.

Abstract: A method and apparatus for trimming a non-volatile memory cell. One method comprising, erasing the memory cell below a desired voltage threshold (Vt) level, applying a program pulse to the memory cell, reading the memory cell, comparing a current conducted by the memory cell with an externally provided reference current using a sense amplifier that is internal to a memory device that contains the memory cell, producing a digital output based on the comparison of the currents and applying successive program pulses until the digital output changes from one logic state to another.

Abstract: Methods for forming multiple dielectric layers at low temperatures include forming a number of metallic layers on a substrate and oxidizing the metallic layers to different dielectric oxides. Oxidation is performed one layer at a time, or all layers together. Dielectric layers thus formed have multiple different oxides in layers, reducing defects, providing high capacitance, and low leakage currents.

Abstract: A sliding power switch is provided. The switch includes a power interface module having a first power port, a second power port and a third power port. The switch also includes a shunt adapted to engage with the power interface module in a first position so as to provide a first electrical path from one of the first, second, and third power ports to another one of the first, second, and third power ports and a second position so as to provide a second electrical path from one of the first, second, and third power ports to another of the first, second, and third power ports. The switch further includes a shunt retainer coupled to the shunt and adapted to aid in placing and removing the shunt from the first and second positions and a slide actuator adapted to engage with and enable the shunt retainer to slide from the first position to the second position.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of addressable blocks. Control circuitry is provided to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks. The control circuitry performs the write or erase operation in response to an externally provided command sequence and prohibits the write or erase operation if an externally provided bank address changes during the externally provided command sequence.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory device comprising an array of memory cells arranged in addressable blocks and an n-bit status register. The memory includes a control circuit coupled to the n-bit status register to program a first bit of the n-bits to a first state indicating if a program operation is being performed on the array. The control circuit further programs second and third bits of the n-bits to identify one of the addressable blocks while the array is being programmed. A method of operating a memory device includes initiating a write operation on a first programmable location of the memory device using a first processor, and reading a status from status data stored in the memory device during the write operation. The status indicates an identification of the first programmable location.

Abstract: Clock generator circuits containing a delay circuit having at least one delay element and at least one bypass are arranged to activate the bypass in response to a first logic level presented at the input of the delay circuit and to deactivate the bypass in response to a second logic level presented at the input of the delay circuit. Such clock generators are useful in synchronous memory devices for generating internal clock signals of fixed pulse width from an external clock signal. The internal clock signal is generated from a triggering event, such as a rising edge of the external clock signal, and has a pulse width determined by the delay time of the delay element. The first logic level is generated in response to the beginning of an output pulse of the clock generator.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to apply erase voltage pulses to the non-volatile memory cells and perform erase verification operations. A pulse counter is coupled to count the erase pulses applied to the non-volatile memory cells. A programmable erase pulse register has been described that indicate a number of initial erase pulses that can be applied to the non-volatile memory cells during an initial verification operation prior to performing a scan operation of the memory block. The control circuitry can also apply additional erase pulses following subsequent erase verification operations. A second programmable erase pulse register is provided to indicate a number of subsequent erase pulses that can be applied to the non-volatile memory cells before performing additional scan operations.

Abstract: A photolithographic mask includes a substrate having a single masking layer from which are formed regions of phase shifting between the substrate and the masking layer and regions of non-phase shifting between the substrate and the masking layer. The photolithographic mask is formed using a single masking layer with binary mask technology in one set of regions and attenuated phase shift lithography in a second set of regions.

Abstract: A system and method for accessing a number of communication lines by one or more testing devices is disclosed. Each of the communications lines is coupled through the system and includes a first termination at a first telecommunications termination site and a second termination at a second telecommunications termination site. The system includes a number of line access devices, each of which is coupled to at least one of the communication lines terminating at the first telecommunications termination site and at least one of the communication lines terminating at the second telecommunications termination site. The system further includes a test device interface, signal direction circuitry, a communications device that facilitates remote access to the test access system by a remote processing unit, and a control device.

Abstract: Memory chips containing multiple-bank memory devices are arranged to be mounted in a memory package with the major axis of the memory chip aligned substantially parallel with the major axis of its memory package. Memory devices of various embodiments contain banks of non-volatile flash memory cells and have access commands synchronized to a system clock. Data chip bond pads for coupling to data pins of a memory package are located in a first quadrant of the memory chip. Address chip bond pads for coupling to address pins of a memory package are located in an opposite quadrant of the memory chip.

Abstract: Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and array architecture. The floating-gate memory cells may be programmed using band-to-band tunneling. The floating-gate memory cells may be read using capacitance sensing or forward current sensing techniques.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: A apparatus for providing a Fast Fourier Transform (FFT) and an inverse FFT is provided. The apparatus comprises a radix-N core. The radix-N core includes at least N multipliers. The radix-N core also includes a twiddle-factor lookup table that stores complex twiddle-factors. The twiddle-factor lookup table is coupled to one input of each of the multipliers. The radix-N core also includes a conversion random access memory (RAM) that stores transform points. The conversion RAM is coupled to another input of each of the multipliers. The radix-N core also includes an array of at least N-times-N adder-subtracter-accumulators.

Abstract: A method for controlling gain in a network is provided. The method includes receiving signals for transmission over a network and adjusting the level of the received signals. The method further includes inserting an additional signal indicative of the level adjustment and transmitting the signals and the additional signal over the network. The method also includes extracting the additional signal after transmission over the network and compensating for the level adjustment based on the extracted signal.