Abstract: Methods and apparatus are described for capacitively signaling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signaling, and reduces or eliminates the requirements for exotic metallurgy.

Abstract: A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.

Abstract: A parallel computer comprised of a plurality of identical processors, each processor having control and data inputs and outputs for communication with the host computers and separate interprocessor inputs and outputs for communication between the processors. The processors are permanently interconnected through interprocessor communications routers into a first, single n-cube array for purposes of interprocessor communication. The data and control inputs and outputs of the processors are separately connected in parallel to the host computers through a resource allocation means to divide the first, single n-cube array of processors into a multiplicity of smaller second arrays controlled by selected ones of the host computers.

Abstract: A chip array comprising a plurality of integrated circuit chips. Each chip comprises a plurality of processors, each processor including a data generation circuit for generating data and data receiving circuit for receiving data, a plurality of on-chip links for interconnecting the processors on each chip to form a processor array on the chip to facilitate the parallel transfer of data generated by the processors along selected directions in the processor array during a parallel data transfer operation, and a plurality of sets of selectively-energizable data transfer terminals. Each set of the data transfer terminals facilitates the transfer of data transmitted by processors along an edge of the processor array defined on the chip, between chips along a selected direction in the chip array during the parallel data transfer operation, with at least one set of data transfer terminals facilitating the transfer of data along at least two non-collinear directions in the chip array.

Abstract: A router comprising a plurality of routing nodes interconnected by a plurality of communications links in a multi-dimensional pattern for transferring messages, each message including an address including a series of address digits each associated with one of the series of dimensions. Each router node includes a switch circuit for selectively coupling messages, received from a communications link associated with a dimension, over a communications link associated with a dimension in accordance with the address. The switch circuit includes a series of message coupling circuits each associated with a dimension, each message coupling circuit being connected to receive messages from a communications link associated with a preceding dimension and to transmit messages over the communications link of the associated dimension, each message coupling circuit further being connected to the message coupling circuits of proximate dimensions.

Abstract: A parallel processor is disclosed which combines the advantages of an array of bit-serial processors and an array of word-oriented processors. Further, the invention provides for ready communication between data organized in bit-serial fashion and that organized in parallel. The processor comprises a plurality of word-oriented processors, at least one transposer associated with each processor, said transposer having n bit-serial inputs and m bit parallel outputs and a bit-serial processor associated with each bit-serial input of the transposer. The parallel processor further comprises a memory for each bit-serial processor and a data bus interconnecting the memory, the bit-serial processors and the bit-serial inputs of the transposer. The transposer converts serial inputs to parallel, word organized outputs which are provided as inputs to the word-oriented processors.

Abstract: A parallel computer system includes a parallel processing array for connection to a control processor to form a parallel computer. The processing array includes a plurality of processing elements that perform processing operations to process data and generate messages, each including an address, in response to commands from a control processor, and that generate status information reflecting the status of their processing operations. A communications network transfers the messages among the processors in accordance with the address information. A control processor generates commands for transmission to the processing elements in parallel to control the processing operations by the processing elements in response to the condition of composite processing status information to facilitate selection of commands to be transmitted to the processing elements.

Abstract: A parallel computer comprises a processor array, a router, a grid interconnection arrangement and a control circuit for controlling the elements in parallel. The processor array comprises a plurality of processors, each processor including a data generation circuit and a data receiving circuit. The data generation circuit selectively generates messages, each including an address, and data in response to data generation control signals from the control circuit. The data receiving circuit receives messages and data in response to receiver control signals from the control circuit. The router is connected to the data generation circuit and data receiving circuit of the processors in the processor array for facilitating, in response to router control signals from the control circuit, the transfer of messages between said processors in the array in accordance with the respective addresses.

Abstract: A message packet router is describes that performs the functions of determining if a message packet is addressed to circuitry associated with the router, of routing message packets to their destination if possible and of storing message packets that cannot be routed on because of circuit conflicts. The router also provides additional functions of merging message packets addressed to the same destination, of saving the state of the router at each significant point in the message routing cycle, and of running the entire routing cycle backwards. This later feature makes it possible to broadcast message packets selectively to certain processors in the array.