Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.

Abstract: An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: A power converter is comprised of a hysteretic controller including a feedback circuit that monitors the output frequency of the controller, compares it to a reference generated either internally or externally by the user, and then adjusts the hysteresis of the controller accordingly. The adjusted hysteresis levels will then cause the switching frequency to either increase or decrease thereby controlling the switching frequency of the power supply controller and maintaining it at a desired level.

Abstract: A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

Abstract: An efficient back bias (VBB) detection and control circuit make possible a low voltage memory device and includes an on-chip VBB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (−(|2VTP|+VTN)) during power-up and a second voltage level (−|2VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

Abstract: An efficient back bias (V.sub.BB) detection and control circuit make possible a low voltage memory device and includes an on-chip V.sub.BB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (-(.vertline.2 VTP.vertline.+VTN)) during power-up and a second voltage level (-.vertline.2 VTP.vertline. during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

Abstract: A synchronous dynamic random access memory (SDRAM) improves memory access time by incorporating into the column address path a bidirectional column factor counter.

Abstract: A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

Abstract: A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.