Abstract: A computer system that has a bus is provided with a host memory coupled to the bus, this host memory having an event status queue in which events are stored. A peripheral controller is coupled to the bus and writes a termination marker in a first block in the memory and events occurring in the computer system in blocks in the event status queue in a first direction beginning with a block adjacent to the first block. A host processor is also coupled to the bus. The host processor reads the written events in a second direction opposite to the first direction beginning with a last block in which an event was written by the peripheral controller. The host processor terminates the reading of events when the first block in which the termination marker is reached. The use of a termination marker allows both the hardware of the peripheral controller and the software run by the host processor to operate in the event status queue at the same time, with no danger of running over each other.

Abstract: A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and a multi-channel DMA controller arrangement coupled to the system interface bus and having multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction. The status queue is searched for an entry in the status queue which indicates whether its corresponding buffer is a free buffer, when a DMA transaction is to occur over one of the DMA channels.