Abstract: A radiation thermometer has a detector for receiving radiation energy from a target object, and the detector generates an AC signal as a result of movement of a chopper. The AC signal is rectified by a rectifying circuit and the rectified signal is supplied to a microcomputer. On the other hand, temperatures around the detector are detected by a temperature sensor and the temperature of the target object is measured based on those detected values. In addition, the radiation thermometer has various calibration modes other than a measurement mode. In a calibration mode I, calibration data concerning a difference in characteristics of the temperature sensor for each thermometer is obtained. Data for correcting timing for synchronous rectification by the rectifying circuit is obtained in a calibration mode II. Calibration data for calculation of the temperature of the target object is obtained in a calibration mode III.

Abstract: A device for manipulating visual images such as those provided by a common slide projector, employing an audio transducer apparatus for controlling positioning of a mirror in response to vertical and horizontal control signals. Numerous control signals indicative of human operator movement are developed by a joy-stick control apparatus for selective application as vertical, horizontal and brightness control signals to the projector transducer system. Selectible automatic control capability is also provided by means of oscillator circuits, float circuitry and automatic brightness control and blanking circuitry.

Abstract: An integrated circuit package having a lead frame positioned between two lead glass layers on a ceramic base and a ceramic window frame bonded to the lead glass for accommodating a cap attached by a glass to gold to gold-tin eutectic bond. The various layers are applied by an advantageous combination of screen printing and fusing steps.

Abstract: A charge coupled device shift register memory structure wherein the shift registers may be selectively activated. Each shift register is clocked by a common set of clock phase electrodes. Individual inhibit lines are placed over each shift register channel, and by applying appropriate voltages to these inhibit lines shifting of data in the underlying channel is prevented. In one embodiment, a channel decoder, common source and drain lines and cooperating gating circuitry facilitate read/write and refresh operations.

Abstract: A content addressable memory system for accessing blocks of data stored in circular charge coupled shift registers in response to a tag word presented to a directory unit comprising circular charge coupled shift registers. The memory includes clocking and logic circuitry for providing selective, high speed clocking of blocks and directory unit registers for both read and write operations. Additional logic facilitates masked directory searches at selective clock rates. Automatic synchronization of fast and slow clocked registers is provided by a counter of predetermined count corresponding to the formula N/(1-H) where H is the number of bits per circular register and H equals the ratio of slow to fast shift rates. A use bit register in the directory unit and a bookkeeping loop register in each module further aid in synchronization of the memory operation.

Abstract: An extendable memory organization capable of last-in-first-out or first-in-first-out operation comprising a stack of charge coupled device shift registers arranged such that each register shifts data in a direction opposite to that of its adjoining neighbors in the stack. Gating interconnecting the registers is selectively operable to enable read and write operations at either of the stack and up or down shifting of data in the stack. In particular, the gating and control structure permits refreshing the memory by alternately shifting each stored data word up and down between two storage positions in the stack. In one embodiment, gating and control is implemented in a sandwich structure incorporated into the charge coupled shift register channel.

Abstract: A power supply system for use in conjunction with digital systems and particularly adapted to avoid impairment of digital system performance by power supply generated noise. The clock frequency of the digital system is monitored, divided and then applied to control the switching frequency of a D.C. to D.C. power converter. The converter thus switches at a synchronized submultiple of the digital clock frequency such that switching transients are confined to transition times within the digital system.

Abstract: An electromagnetic circuit for controlling the travel of a stylus by attaching the stylus to a movable core. The movable core cooperates with a drive coil to form a magnetic circuit with annular portions extending into the drive coil from both ends thereof.

Abstract: A fixture for interfacing electrical leads with the terminal edges of a printed circuit card, having a frame for supporting the card, a fixed connector for receiving one of the card's terminal edges and a movable connector slidably mounted on the frame and responsive to the operation of an actuating member for mating with the card's second terminal edge while simultaneously forcing mating of the fixed connector and first terminal edge. As mating occurs, resilient fingers mounted in conjunction with the second connector and previously cammed away from the card engage apertures in the card. These fingers serve to extract the card from the fixed connector when the movable connector is actuated away from the fixed connector toward a stop. At the stop, the fingers are cammed out of the apertures, and the progression of the card is halted while the movable connector continues its motion and thereby decouples from the then stationary second terminal edge.

Abstract: A stack memory having a last-in-first-out memory organization comprising a plurality of pairs of two-phase charge coupled device shift registers arranged into a plurality of rows, the CCD registers of each pair being interconnected by digital logic to provide a circular shift register cell and to direct data into and out of the cell. Each cell is interconnected through its logic to an adjacent cell within the same row, and each row of a plurality of circular shift register cells is interconnected between an input buffer register and an output buffer register. The input buffer register is used to write data into each one of the plurality of rows of cells, and the output buffer register is used to retrieve the data from each row of cells.