Abstract: A memory module containing addressable memory devices, and the circuits necessary to address and drive these devices, is configured so that a trade-off between memory size and word length can be made by rewiring the backplane. Thus, a single memory module design can be used for a variety of computer memory applications. This is accomplished by incorporating on the module a complete set of addressing and signal driving circuits, and allowing for the control of these module components through a system of control lines wired through the backplane.

Abstract: A microprocessor with a bus structure for carrying address and data signals wherein an address may be modified by an index value for indirect addressing by deriving said index value from an index register or a control word field. Immediate addressing is provided on branch instructions by providing two separate incrementing paths to avoid loss of a machine cycle during branch.

Abstract: Circuits for the improved operation of microprogrammable computers are described. This improvement is accomplished by providing a set of read-only memory devices for storing the micro-code for all combinations of arithmetic logic unit function, carry bit and file register address than can be specified by an instruction word executed from Main Memory. In a universal microprogram designed to execute that family of Main Memory instructions that differ only in the functions specified above, the instruction word is used to address the read-only memory devices, the micro-code output of which is used to control the file, carry in bit and arithmetic logic unit. Through the use of these circuits a family of instructions may be executed by a single microprogram and at no increase in execution time over that required for the execution of a microprogram dedicated to a single instruction.

Abstract: A Read-Only Memory device in the CPU of a microprogrammable computer contains a diagnostic program suitable for self-testing the computer. A microprogram for loading this diagnostic program from the Read-Only Memory device into Main Memory is contained in the Control Memory of the CPU. When required, the diagnostic program is loaded into Main Memory and executed thus allowing for the testing of a computer without the need of operational peripherals.

Abstract: A microprogrammable data processor comprising a generalized three-bus archictecture wherein the functional processing elements are connected between the busses by means of tri-state logic elements which allow the elements to selectively drive, receive from, or present a high impedance to the busses under control of a microprogram. The device includes an input-output system in which the input/output device may have access to all three busses, two for data and for address inputs and the third for receiving output data. The busses may be multifunction busses for carrying either data or address signals.The device utilizes a single phase clock and performs operations in a highly parallel manner.

Abstract: Data processing and computer systems require continuous monitoring of the primary alternating current power. A power failure must be detected very quickly (within a fraction of a cycle), so that the contents of a volatile memory can be quickly converted into a nonvolatile form. This must occur before power system storage is expended and control is lost. RMS power direction is developed by the product of voltage and current with an integrated circuit multiplier device. When power fails, the circuit indicates a power flow reversal or power equals zero from the detected system current times voltage factor. A retriggerable one-shot in conjunction with a NAND gate is utilized to detect the instantaneous voltage drop to zero and current reversal in order to energize other circuits to protect such volatile data in the event of a power failure.

Abstract: A digital line receiver circuit which incorporates a slope detector in the form of a differential voltage comparator. The two inputs to the comparator receive a composite digital video signal but the signal on the second input is modified by a delay and biasing arrangement such that the output gives a representation of the time positions of polarity changes of the digital input.