Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.
December 18, 1998
Date of Patent:
January 30, 2001
Texas Instruments Incorporated
Amitava Chatterjee, Richard A. Chapman, Syed Suhail Murtaza
Abstract: Generally, and in one form of the invention, a method is presented for the photo-stimulated etching of a CaF2 surface 12, comprising the steps of exposing the CaF2 surface 12 to an ambient species 16, exciting the CaF2 surface 12 and/or the ambient species 16 by photo-stimulation sufficiently to allow reaction of the CaF2 surface 12 with the ambient species 16 to form CaF2 ambient species products, and removing the ambient species 16 and the CaF2 ambient species products from the CaF2 surface 12. Other devices, systems and methods are also disclosed.
Abstract: A current folding and interpolating circuit (80) in an analog-to-digital converter (10, 152) has L folders, each of them includes M differential pairs (82, 84), each having N first transistors (86-89, 100-103) biased by an input voltage and N second transistors (90-93, 96-99) biased by a reference voltage, and a current source (110, 112) coupled to the source terminals of the first and second transistors. The second transistors of different differential pairs are biased with different reference voltages. Selected drain terminals of the first transistors (89) of one folder (82) are coupled to selected drain terminals of the first transistors (100) of at least one other folder (84), and selected drain terminals of the second transistors (93) of one folder (82) are coupled to selected drain terminals of the second transistors (96) of at least one other folder (84). More than one interpolated signals may be generated between two folders.