Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using selective etchants consecutively until the metal layers over the bond pads are removed without damaging the copper metallization. Replacement metal layers are finally deposited over the bond pads. Specifically, the bondable metal, such as gold, is selectively removed by a cyclic dithio-oxamine compound, dissolved in tetra-hydro-furane or acetone. The barrier metals, such as nickel and palladium, are removed by a mixture of inorganic and organic oxidizing acids.

Abstract: Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format allows better automation of the molding process using equipment and fabrication technology known in the industry, and provides a cost effective solution to assembly of high density area array packages. The design of heat spreaders include reduced cross section connecting straps which are readily severed and leave only a small plastic to metal interface for ingress of contamination. Further the designs comprehend either embedded or exposed heat spreaders with methods to hold securely during the molding process.

Abstract: A wafer-scale assembly apparatus for integrated circuits and method for forming the wafer-scale assembly. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.

Abstract: A semiconductor package substrate for assembling an integrated circuit chip operable at fast ramp rate signals and clock rates, comprising an insulating support having a region for attaching said chip; a pattern of electrical interconnections, disposed on said substrate in one metallization level and operable for transmitting waveforms; and a low pass filter for removing unwanted high frequency components from said transmitted waveforms, comprising a network of inductors and capacitors formed within said one metallization level and positioned substantially within said substrate region for chip attachment.

Abstract: A dicing saw blade assembly with parallel blades separated by a spacer and attached to a single spindle on an automated dicing saw, is applicable to precisely separating CSP or MCM devices which have been fabricated on a polymeric substrate. Two parallel cuts are made simultaneously in the scribe streets of the substrate to separate the flip chip devices. The substrates are diced from the bottom side, thereby allowing use of thin blades for separating devices having relatively thick chips, as well as chips with attached heat spreaders.

Abstract: A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.

Abstract: A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.

Abstract: A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semiconductor integrated circuits having a plurality of leads, portions of said leads comprising undulating patterns and a surface metallurgy for promoting solder wetting, said leadframe being disposed between said first and second chips, and said active surface of said first chip positioned in front of said active surface of said second chip; and connections between each of said contact pads of said first chip to one of said leads, respectively, and between each of said contact pads of said second chip to one of said leads, respectively, said connections comprising solder balls, whereby the connections to at least one of said leads are common between said first and second chips.

Abstract: An architecture and method of fabrication for an integrated circuit 200 having a bond pad 208; at least one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via 205; a combination of a bondable metal layer 207, a stress-absorbing metal layer 203, and a mechanically strengthened, electrically insulating layer 204; and said combination of layers separating said contact pad and said portion of said integrated circuit, and having sufficient thickness to protect said circuit from bonding impact.

Abstract: A leadframe for use with integrated circuit chips Comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment; and a plated layer of solder on said nickel layer, selectively covering areas of said leadframe intended for parts attachment.

Abstract: The invention relates to packages of semiconductor devices, specifically of the surface mount and Quad Flat Pack families, that can be used in current semiconductor device production, and to a method of automated testing. The packages have a plurality of insulating tie bars supporting a multitude of leads. The tie bars are designed so that they comprise celectrically conductive vias in a pattern expanding the effective lead pitch for more convenient testing, without introducing unwanted side effects. The full benefit of the expanded lead pitch can be exploited during the electrical testing of the device which utilizes a test apparatus simplified for an automated testing procedure. The base of the apparatus includes a multitude of electrically conductive and mechanically elastic passageways with surface contours adapted for contacting the metallic end connectors of the semiconductor device-to-be-tested, as well as the metallic connector to the tester.

Abstract: A process for the fabrication of an integrated circuit assembly, using thin film platinum metallization to provide edge-side contacts suitable for solder ball connections. Three-dimensional laser ablation may be used for patterning metal films. A multi-chip assembly may be formed using orthogonal edge-side mounting on a substrate.

Abstract: A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the integrated circuit, a dielectric layer and a second metal layer. The second metal layer is segmented to form multiple capacitors, and each capacitor is interconnected to power supplies of the chip. Interconnection to different integrated circuit packages is provided. A method of making the semiconductor device is also disclosed.

Abstract: A semiconductor wafer is disclosed comprising a substrate having a surface carrying an array of integrated circuit chips bordered by dicing lines; at least two sets of substantially parallel structures within each of said dicing lines, each set extending along the edge of a chip on opposite sides of each dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively, and a sacrificial composite structure in combination therewith, between said wall and the center of the dicing line, said composite structure including means of dispersing the energy associated with crack propagation, whereby any crack having sufficient energy to penetrate the composite structure will be transformed into a plurality of weaker cracks, non of which will be capable of penetrating said wall.

Abstract: A double sided electrical connection flexible circuit particularly useful as a substrate for an area array integrated package, and the method of fabricating the structure is described. A circuit having interconnections on one surface and solder ball contact pads on the second surface are interconnected by copper plated from a single surface in order to avoid entrapment of air pockets. In one embodiment, the conductive vias are formed from a copper film which extends from the solder ball contact pads, which may be indented, providing a well for solder balls in the contact pad.

Abstract: A semiconductor device comprising a thermally conductive foil including a chip mount portion having first and second surfaces; an integrated circuit chip attached to said first surface; a body of encapsulation material molded around said chip and said first surface such that it leaves said second surface exposed; and said second surface comprising means for forming thermal contact, thereby creating a path for dissipating thermal energy from said chip. Said means for thermal contact comprise a configuration of said second surface suitable for direct thermal attachment to a heat sink. Alternatively, said means for thermal contact comprise a configuration of said second surface suitable for thermal attachment including solder balls between the chip and the heat sink.

Abstract: A packaged semiconductor device with electrical redundancy for improved mechanical reliability and a method for fabrication are disclosed. The device comprises a semiconductor chip having an integrated circuit, said circuit having a multitude of electrical terminals with metal contact pads; an interposer of electrically insulating material having electrically conductive paths extending through said interposer from one surface to the opposite surface forming electrical entry and exit ports on said insulating interposer; said interposer with its entry and exit ports having regions of different mechanical stress levels; each of said chip contact pads being electrically connected to a respective entry port of said interposer and by means of said conductive paths to at least one respective exit ports; and at least one of said entry ports being electrically connected to a plurality of high-stress exit ports in parallel.

Abstract: A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface including at least one dimple having a suitable size and shape to receive a solder ball or solder paste; and said dimple having an electrically conductive solderable surface connected to said terminal.

Abstract: A video wire bonder system includes a processor (12) coupled to an imaging station (14), an input device (16), a display (18), and a memory (20). Processor (12) generates an image overlay (30) having a graphical representation of each video wire bond between a bonding pad (34) of a semiconductor die (21) and a lead finger (35) of an associated lead frame (22). Processor (12) generates a template (28) comprising an organization of video wire bond parameters associated with each video wire bond, and stores template (28) in memory (20). Display (18) displays image overlay (30) to provide visual feedback to an operator while the operator is programming template (28).

Abstract: A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.