Abstract: A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control circuit (106) and a output stage bias reference circuit (108). The input gain stage (102) includes differential inputs (IN−, IN+) and differential outputs (A1, B1). The output stage (104), having control transistors, connects to each differential output (A1, B1) of the input stage (102). and a quiescent current control circuit (106) deriving common mode feedback control signal (VCS1) from the differential outputs (A1, B1) and voltage bias node (D1). A quiescent current control circuit (106) derives the common mode feedback control signal (VCS1) to maintain the voltage of the input gain stage transistors (M3, M4) at a desired level.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.