Abstract: The present invention provides, in one embodiment, process of treating a target semiconductor surface. The process includes exposing a test surface to a plasma protocol (110), and measuring chemical changes in discrete locations of the test surface (120). The process further includes preparing a target surface by exposing the target surface to the plasma protocol (140) when a uniformity of the chemical changes are within a performance criterion of the plasma protocol (130). Other embodiments advantageously incorporate this process into methods for making semiconductor devices and integrated circuits.

Abstract: A protective device (3) for a hermetic type electromotively driven compressor (1a) includes a protector assembly (30) having a housing (32) with an electric current fuse (34) which detects a predetermined over-current. The housing (32) comprises an electrically insulating skirt member (31) formed so as to block a conductive part on the side facing an external connection terminal. By forming the electrically insulating skirt member (31) of housing (32) for a hermetic type electromotively driven compressor, insulation distance between a conductive part such as the electric current fuse (34) and an external conductive part such as a metal wall part (21) is set to be 9.5 mm or more.

Abstract: An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and ringing while allowing for higher data rates. The discharge circuit is turned on after the head voltage or current reaches an overshoot condition. In preferred embodiments, the discharge circuit includes variable discharge capability by selecting one or more parallel drive transistors or varying a variable delay in the discharge circuit or any combination of both variables. Both can be controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis.

Abstract: The invention is a method for attaching an electronic component (40) having Ball Grid Array contacts (36) to a circuit board contact array (31) to prevent the solder balls (36) of the Ball Grid Array from fracturing and distorting during solder reflow when the Ball grid Array contact (36) is attached to a contact (31) on a printed circuit board (30) that has a via (32) extending at least partially though the printed circuit board (30). A solder form (35) is placed over each via (32) in each contact (31) of the contact array. The electronic component (40) that has BGA contacts (36) is placed over the contact array (31) such that each ball (36) of the ball grid array of the electronic component resides on a solder form (35). The component (40) and circuit board (30) is subjected to a solder reflow process to seal the component (40) to the circuit board (30). The solder form (35) at least partially fills the via (32) preventing the BGA contact (36) from collapsing into the via (32).

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: A control circuit for motor current including a circuit to generate a voltage to indicate the actual motor current, a first convert circuit to convert the voltage indicative of the motor current to a current, a compare circuit to compare the current indicating the motor current with a reference current and generate a difference current between the current indicating the motor current and the reference current, and a second convert circuit to convert the difference current to a voltage to indicate a difference in motor current from the reference current.

Abstract: An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Abstract: A method for N-best search for continuous speech recognition with limited storage space includes the steps of Viterbi pruning word level (same word, different time alignment, thus non-output differentiation) states and keeping the N-best sub-optimal paths for sentence level (output differentiation) states.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A computer uses an environmental manager (20) to detect and respond to changing environmental conditions, in order to enhance and simplify a users interaction with the computer. Environment changes are detected by a plurality of informants (22), each of which has a specified function. Informants communicate through a CIM (26). The CIM (26) establishes communication channels with each informant regarding which information will be provided by the informant and which information that informant needs from other informants. Informants (22) may receive environmental information from a number of sources, including physical location detectors, hardware configurations, software configurations, and network connections. As environmental conditions change, the informants and applications may respond to the changes. A particular capability to respond is the autolaunch capability which detects user behavior and uses this knowledge to automatically load a program responsive to changing environmental conditions.

Abstract: A television receiver (10) that has a spatial light modulator (15) and a projection lens (17a) and that projects images to a screen (18). If the aspect ratio of the image to be displayed does not match that of the spatial light modulator (15), an anamorphic lens (17b) is positioned in the optical path of the image, between the projection lens (17b) and the screen (18). In this case and in typical applications, the spatial light modulator (15) generates an image that is anamorphically squeezed in the horizontal dimension, and the anamorphic lens (17b) widens the image so that the viewer perceives a normal wide-screen image on the screen (18).

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A testing system includes a testing hardware subsystem which can perform testing under a plurality of testing modes. Each testing mode corresponds to the operation of a particular version of a tester. A control subsystem is coupled to the testing hardware subsystem. The control subsystem can direct the testing hardware subsystem to test under one of the plurality of testing modes at a given moment.

Abstract: In a fast adaptive filter unit, an update unit replaces the multiplier unit which generates a product of the filter constant, the error signal and data signal and adding this product to a previously generated coefficient with a reduced complexity unit. The reduced complexity unit determines the sign of the product and whether the product is zero or non-zero. As a result of this determination a two bit signal is generated which is used to either increment or decrement the count in a register in the counter unit. The count held by the register is the coefficient signal, the coefficient signal being updated by each additional operation. In order to prevent the register from over-flowing, a second counter applies a signal periodically to the counter unit which decrements the magnitude of coefficient signal stored in the register by one count.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.