Abstract: An improved bias circuit for a disk drive head which reduces or eliminates transients while switching biasing. Embodiments of the invention are directed to eliminating transients while switching the bias of a MR head such as from current bias to voltage biasing. In an embodiment of the present invention, bias enable signals from a control circuit are inputs to delay circuits. The delay circuits provide a delay on the high-to-low transition, and essentially no delay on the low-to-high transition. The unsymmetrical delay ensures that the read head bias current will continue to be driven during the biasing transition to reduce voltage swings that could damage the head.

Abstract: In order to measure the power consumed by a central processing unit during execution of a software program, the trace components are used to determine the input signals and the output signals and interrupt conditions for each clock cycle. The input signals and the output signals can be applied to a simulation model of the central processing system to determine the state of the central processing unit for each clock cycle. The simulation model is also used to determine the power dissipated for each state. Combining the knowledge of the progression of states of the central processing unit with the power consumed by the central processing unit for each state, the consumption of power by the central processing unit can be determined as a function of execution of the program. By comparing the power consumed with the portion of the program being executed, the program can be adjusted to reduce the power required during the execution of the program.

Abstract: A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal, (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).

Abstract: A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed outwardly of the first oxide layer. A second oxide layer is formed outwardly of the nitride layer. A trench is formed through the first oxide layer, the nitride layer, and the second oxide layer and into the semiconductor layer. With the second oxide layer protecting an upper surface of the nitride layer, the nitride layer is etched to form a lateral recessed side boundary of the trench at the nitride layer. The shallow trench isolation layer is formed in the trench.

Abstract: The present invention provides a system and method for processing low voltage threshold transistors on a semiconductor wafer. The method may include: forming core transistors with drains on the semiconductor wafer; forming low voltage threshold transistors with drains on the semiconductor wafer; forming input output transistors with drains on the semiconductor wafer; forming a spacing layer over the core, low voltage and input output transistors; forming a first photoresist mask layer over the low voltage transistors; doping the drains of the core and the input output transistors, wherein the doping is a medium doping; forming a second photoresist mask layer over the input output transistors; and doping the drains of the core and the low voltage threshold transistors, wherein the doping is a medium doping.

Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Abstract: An unsafe detection circuit for detecting a kickback signal including an input circuit for inputting a kickback signal, a circuit for detecting the presence or absence of said kickback signal, and a fault detection circuit to respond to said presence or absence of said kickback signal to provide an indication of a fault.

Abstract: A highly efficient multi-phase power system having both reduced size and reduced cost. The multi-phase power system includes a plurality of Pulse Width Modulation (PWM) controllers. A first controller is programmed to function as a “master” controller, and the remaining controller(s) are programmed to function as “slave” controllers. Each controller includes a synchronous counter and control logic circuitry. The control logic generates at least one synchronization output signal based on the outputs of the counter and the programming state (i.e., master or slave) of the controller. The master controller generates a master clock signal having a synchronizing state encoded thereon and provides the master clock to the slave controller, which includes synchronization circuitry for receiving the master clock and resetting the counter based on the synchronizing state of the master clock, thereby assuring that appropriate phase relationships are maintained between the controller outputs.

Abstract: A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

Abstract: A system and method is provided for enabling the reuse of algorithms in multiple application frameworks with no alterations required of the algorithm once it is developed. An inverted memory allocation mechanism enables various algorithm modules to be integrated into a single application without modifying the source code of the algorithm modules. A plurality of algorithm modules is combined with a framework to form the software program. Each of the plurality of algorithm modules has a memory interface which responds to a memory allocation inquiry with memory usage requirements of an instance of the algorithm module. The software program is then loaded on a hardware platform and executed. During execution, the framework sends a query to the memory interface of each of the plurality of algorithm modules to request memory usage requirements for each instance of each of the plurality of algorithm modules.

Abstract: An improved DMD type spatial light modulator having an array of pixels (18). The pixels (18) are of the “hidden hinge” design, each pixel having a mirror (30) supported over a hinged yoke (32). Addressing electrodes (26, 28) on an underlying metallization layer and addressing electrodes (50, 52) at the yoke level provide electrostatic forces that cause the mirrors to tilt and then to return to their flat state. The pixels (18) are designed to provide increased clearance between the leading edge of the yoke (32) and the underlying metallization layer when the mirrors (30) are tilted. Various features of the improved pixel (18) also improve the contrast ratio of images generated by the DMD.

Abstract: A data communications subsystem (15) including a digital signal processor (DSP) (20) for performing bit insertion to preclude the inadvertent serial transmission of a protocol flag sequence is disclosed. A trigger sequence detection process (40) applies an infinite impulse response (IIR) filter to a current sequence of the input bitstream to generate a insertion bitstream that is bit sychronized with the the input bitstream. A bit insertion process (50) then inserts bits into the input bitstream at bit positions indicated by the insertion bitstream. The trigger sequence detection process (40) may be applied to subsequent sections of the input bitstream, as it is not dependent upon the results of the bit insertion process (50).

Abstract: In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions. A debug event detector detects predetermined debug event. Upon detection of a debug event, the in-circuit-emulator suspends program execution except for real time interrupts. An emulation monitor program permitting visibility into the state of the integrated circuit is run as such a real time interrupt interrupt. The integrated circuit includes a serial scan path for control of the state of the integrated circuit, such as a JTAG interface. The in-circuit-emulation selectively assigning emulation resources of the integrated circuit to one of the serial scan path or the monitor program. A monitor privilege input controls this assignment by its digital state. The the emulation resource may be a read write data register and he assignment includes accessing the data register.

Abstract: To provide high quality coding with respect to both interlace video and progressive video. It is a coding method for image signals, which includes the steps of dividing the picture elements within 1 macroblock of input image signals into multiple groups, totalling each group as interlace video by executing DCT (block 31), comparing said totalled result and the result of DCT (block 32) executed with respect to the entire picture elements within said 1 macroblock, and selecting one of the DCT results (block 34).

Abstract: In the resistance measuring circuit, a measuring capacitor (Cm), as controlled by a microcomputer (10), is charged in a first cycle to a predefined charging voltage (Vcc) and discharged via a reference resistor (Rref) to a predefined discharge voltage before then being recharged in a second cycle to the charging voltage and discharged via the resistance to be measured (Rs1) to the discharge voltage. The microcomputer (10) measures in each cycle the time duration between the start of the discharge procedure and the point in time of attaining a predefined fixed value of the voltage between the charging voltage and the discharge voltage across the measuring capacitor (Cm). From the product of the reference resistance and the ratio of the time duration measured in the second and first cycle, the resistance value to be measured is determined. There is provided a closed loop (10, 14, 16) for controlling the discharge voltage to a fixed predefined constant value.

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: A filter circuit with two 2nd order stages cascaded in sequence. The first stage is implemented with high quality (Q) factor, and the second stage is implemented with a low Q factor and an imaginary zero. The first stage is designed to further eliminate the unwanted frequency components. The imaginary zero in the second stage eliminates the noise present in the output of the first stage due to the requirement of high Q in the first stage. Any additional noise introduced by the second stage is minimal due to the low Q of the second stage. Each stage may be implemented using only a single operational amplifier when the first stage generates a differential output signal.

Abstract: A method for removing heat from a spatial light modulator device in a digital projection display by encapsulating the device package in a thermal conductive socket attached to a printed wiring board. The socket wraps around the device package to remove both optically generated heat from the front of the device and electrically generated heat within the device. In higher brightness projector applications, fins are added to the socket to increase the mass and surface area of the socket, thereby improving the heat dissipation properties of the system. The heat sink socket attaches to the printed wiring board using a screw attachment means, which also assures electrical connectivity to the spatial light modulator through a interposer element between the device and spatial light modulator. This approach completely eliminates conventional heat sinks, mounting studs, and fasteners, which have been failure mechanisms in these type displays.

Abstract: Iterative parallel interference cancellation estimations for signals received from multiple coded sources or a source with multiple coded outputs with updated estimates of interfering signals used during an iteration.

Abstract: The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 located over a first epitaxial layer 130, wherein the second epitaxial layer includes at least two dopant profiles 143, 147. The vertical bipolar transistor 110 may further include a collector 154, a base 156 and an emitter 158 located over or within the second epitaxial layer 140.