Patents Represented by Attorney, Agent or Law Firm Fredrick J. Telecky, Jr.
  • Patent number: 6785859
    Abstract: An interleaver structure for turbo codes with variable block size. The interleaver permutes symbols through multiplication by a parameter followed by modulus by the block size. A table of the multiplication parameter as a function of the block size permits adaptability to a wide range of block sizes without significant memory consumption.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: August 31, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Haim Goldman
  • Patent number: 6678324
    Abstract: An image information encoding system that includes detecting an image portion for which higher image quality is desired based on the motion vector value and the image error value, calculating a bit rate control value based on the detection result as well as the buffer usage rate, and changing the roughness of the quantization step based on the bit rate control value. The objective is to minimize the degradation of an image due to compression of a still image portion.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: January 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Satoru Yamauchi
  • Patent number: 6651083
    Abstract: A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: November 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Iain Robertson, Amarjit S. Bhandal, John Keay
  • Patent number: 6576519
    Abstract: An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond the gate section on opposite sides thereof. A dielectric layer has an upper surface spaced above the upper ends of the side walls. Contact openings are created through the dielectric layer, so as to expose surface portions on the source and drain regions. Conductive contacts are formed in the contact openings. The portions of the side walls which project above the gate section permit misalignment of the contact openings, without exposing any portion of the gate electrode during formation of either contact opening.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: June 10, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 6553547
    Abstract: A method for generating charge sharing test vectors for a circuit generates a first test vector (120) and a second test vector (122). The method provides a test model (98) including a logic cell (10) and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method generates a first test vector (120) for the test model (98) having an input pattern to discharge nodes of the logic cell (10) and evaluate discharge AND gate (102) to a logic level 1. The method generates a second test vector (122) having an input pattern to evoke the worst charge sharing behavior for the logic cell (10) and evaluate charge sharing AND gate (104) to a logic level 1.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Keerthinarayan P. Heragu, Patrick W. Bosshart
  • Patent number: 6490329
    Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 3, 2002
    Assignees: Dot Wireless, Inc., VSLI Technology, Inc.
    Inventors: Tien Q. Nguyen, John G. McDonough, David (Daching) Chen, Howard (Hau) Thien Tran
  • Patent number: 6402528
    Abstract: An electronic part mounting device including a main socket body (2) having a plurality of contact parts (7) mounted therein for making contact with a plurality of contact terminals (10a) on an electronic part (10). Main socket body (2) is adapted to work with a contact opening and closing tool (3) with a holding part (34) for removably mounting and dismounting an electronic part (10) in the socket body (2) and an actuator member (30) having touch parts (32) that engages and moves a tool positioning part (52) on the socket body (2) to cause opening and closing of contacts (7).
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: June 11, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Hideyuki Takahashi, Toyokazu Ezura
  • Patent number: 6072212
    Abstract: This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 6, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Cetin Kaya, Kemal Tamer San
  • Patent number: 6053617
    Abstract: A process for manufacturing micromechanical devices. The process includes the step of covering the activation circuitry (201) and those parts of the device that come in contact with moving parts with a pad film (202). The pad film prevents frictional wear and sticking of the moving parts, and can prevent electrical shorts between different parts of the activation circuitry. Additionally, the pad film can prevent particulates from interfering with the operation of the device.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: April 25, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Toshiyuki Kaeriyama