Patents Represented by Attorney Fujitsu Patent Center
  • Patent number: 8348568
    Abstract: A fastening structure includes first and second board-like members to be fastened, a stopping and anchoring part for latching these board-like members to be fastened, and a stopping and anchoring part holding board-like member between the first and second board-like members to be fastened. For a hole of a first inner diameter formed in the first board-like member to be fastened, and a hole of a second inner diameter formed in the second board-like member to be fastened, a smaller hole of a third inner diameter is formed in the stopping and anchoring part holding board-like member, and the impact of gap of the member in production tolerance is avoided thus enhancing the fastening function.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventor: Hajime Murakami
  • Patent number: 8349624
    Abstract: A method of manufacturing a semiconductor device, includes providing a mark above a main surface on a semiconductor substrate, separating the semiconductor substrate into a plurality of semiconductor elements by cutting the semiconductor substrate, determining a reference semiconductor element on the basis of a coordinate data indicating coordinates of the mark and coordinates of all of the semiconductor elements on the semiconductor substrate, and picking-out the semiconductor elements on the basis of the coordinate data using a pick-out apparatus. The providing operation includes forming a protective coat onto the main surface of the semiconductor substrate, irradiating a point on the main surface of the semiconductor substrate with a laser beam through the protective coat, and eliminating the protective coat from the main surface of the semiconductor substrate.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshito Konno
  • Patent number: 8351597
    Abstract: The present invention relates to an electronic device that can output received voice and input transmitted voice at the same time and enhances a suppression function for echo due to the received voice sneaking into the transmitted voice. An electronic device (e.g., portable telephone terminal device) outputs the received voice from a voice output unit (speaker), inputs the transmitted voice through a voice input unit (microphone), and includes an echo canceller unit that subtracts a pseudo echo signal for the received voice from the transmitted voice to suppress an echo component in the transmitted voice and a controlling unit that changes an echo suppression amount of the echo canceller unit in accordance with the received voice volume.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Yukihiro Sato, Nobuhiro Mochizuki
  • Patent number: 8349540
    Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Setta, Hiroki Futatsuya
  • Patent number: 8351800
    Abstract: An optical receiver includes a dispersion mitigator configured to mitigate a wavelength dispersion value in an optical signal by using a set dispersion value, a phase difference signal generator configured to generate a phase difference signal by calculating the phase difference between a first clock signal included in an optical signal mitigated by the dispersion mitigator, and a second clock signal, a dispersion value adjuster configured to adjust the set dispersion value set in the mitigator, a controller configured to control fluctuations appearing in a phase difference signal generated by the phase difference signal generator when the dispersion value is adjusted by the dispersion value adjuster, and a clock generator configured to generate the second clock follow up the phase of the first clock, being based on the phase difference signal controlled by the controller.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Kiyotoshi Noheji, Noriaki Mizuguchi
  • Patent number: 8351112
    Abstract: An optical amplifier includes a first amplification medium to receive light obtained by combining signal light input into an input port and the excitation light generated by a light source; a second amplification medium disposed between the first amplification medium and an output port; a loss medium to receive the signal light separated from light output from the first amplification medium; a variable optical attenuator that is disposed on a path that bypasses the loss medium, and to receive the excitation light separated from the light output from the first amplification medium; a first photodetector to detect power of light separated from the signal light transmitted from the second amplification medium; and a controller to control the amount of attenuation for the variable optical attenuator or output power of the light source so that signal light power per wavelength of the signal light becomes closer to a target value.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventor: Tomoaki Takeyama
  • Patent number: 8352700
    Abstract: A memory management apparatus includes: a memory space including a memory area serving as a heap area and a non-heap-area memory area; and memory management unit which add a header for an object to a memory area other than heap-area to treat the non-heap-area memory area as a mock object in order to treat a plurality of heap areas divided by the non-heap-area memory area as a single continuous heap area.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventor: Akira Akiyama
  • Patent number: 8351790
    Abstract: An optical transmission system including: first, second, and third stations; a main transmission path that bi-directionally couples the first station with the second station; and an optical add/drop multiplexer (OADM) disposed on the main transmission path, the OADM branching light from the first and second station, combining light from the third station to the main transmission path; wherein the OADM includes an input determination unit and an optical path switching unit, the input determination unit detects the power of the lights, and determines whether each of the input lights is lost or not, and the optical path switching unit forms a loop-back route based on the determination.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Yuhiro Midorikawa, Izumi Yokota
  • Patent number: 8349147
    Abstract: A method for forming a photocatalytic apatite includes a target production step (S12) for producing a sputtering target that contains photocatalytic apatite, and a sputtering step (S13) for forming a photocatalytic apatite film on a substrate by sputtering using the target. A firing step (S11) for firing the photocatalytic apatite is conducted before the sputtering step so as to increase the crystallinity of the photocatalytic apatite.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Noriyasu Aso, Masato Wakamura
  • Patent number: 8349541
    Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Setta, Hiroki Futatsuya
  • Patent number: 8344521
    Abstract: A semiconductor device includes a semiconductor package, a circuit board, an interconnection electrically connecting the semiconductor package and the circuit board, and a wiring structure. The wiring structure includes a through hole, a contact disposed at the through hole and a lead pattern extending from the contact. The wiring structure is disposed between the semiconductor package and the circuit board. The interconnection passes through the through hole and connects with the contact.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventor: Mitsuo Suehiro
  • Patent number: 8345538
    Abstract: There is provided topology information including connection states among nodes in a network, and port information including restriction conditions on connectivity among ports within a restricted node. A path search apparatus finds a first path having the minimum total link-cost among a plurality of paths. The topology information is changed so that the first path is not searched for as a path having the minimum total link-cost among the plurality of paths, and the port information is changed based on a port connectivity change rule. Then, the path search apparatus finds a second path different from the first path, based on the changed port information and the changed topology information, and reconfigures a pair of link-disjoint paths satisfying the restriction conditions imposed on the restricted node, by removing a link shared by both the first and second paths from the original topology information.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventors: Tomohiro Hashiguchi, Toru Katagiri, Kazuyuki Tajima, Yutaka Takita
  • Patent number: 8342746
    Abstract: A temperature measurement system including a measurement plate placed on a measurement plane specified on at least one of an intake opening and an exhaust opening of a rack storing an information processing apparatus or at a position being away from the measurement plane by a predetermined distance; and an infrared camera configured to capture an image of the measurement plate, where the infrared camera is placed at a position with which the measurement plane is not captured and the measurement plate is captured by the infrared camera.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventors: Atsushi Furuya, Junichi Ishimine, Yuji Ohba
  • Patent number: 8347323
    Abstract: A broker-program generating unit generates a broker program by using an interface-definition-language file defining interface definition information concerning a plurality of applications described in various programming languages. The broker program is installed in a middleware platform that absorbs and hides a common object request broker architecture, and brokers an interaction between the applications with a structure that stores data in a binary format as an interface to the middleware platform.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Honishi, Tokio Nakayama, Yoshiharu Kamata, Shinya Suematsu, Kouichi Hidaka
  • Patent number: 8346306
    Abstract: A suspend control apparatus, disposed in an electronic device having a SIM card, includes a control unit that switches the state of the SIM card between a suspended state and a resumed state. The control unit determines, based on the state of SIM card access for data communication and the state of the SIM card when the data communication occurs, whether to give priority to SIM card access or switching to the suspended state, and sets the state of the SIM card accordingly.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Limited
    Inventors: Masanobu Kawakishi, Mikimasa Yamagishi, Takao Ohta, Shinichi Matsuya, Kiyotaka Sawae, Shinji Yamauchi, Masahiro Harima, Yoichi Kikuchi, Keigo Kuramoto
  • Patent number: 8343830
    Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Patent number: 8345503
    Abstract: A booster circuit includes a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node; a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node; a first switch coupling the third node with a power supply line when the fourth node is set to a first level; a second switch coupling the sixth node with the power supply line when the first node is set to the first level; a third switch transferring a plurality of electric charges of the sixth node to the second node; a fourth switch transferring a plurality of electric charges of the third node to the fifth node; a fifth switch coupling the second node with a voltage line; and a sixth switch coupling the fifth node with the voltage line.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Atsushi Nakakubo
  • Patent number: 8344456
    Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: January 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahito Arakawa, Toshihiko Mori
  • Patent number: 8336756
    Abstract: A reflow apparatus, where formic acid is used for cleaning a surface of a solder electrode on a processing target, is disclosed. The reflow apparatus includes a processing chamber, a formic acid introduction mechanism for supplying an atmosphere gas containing formic acid to the processing chamber, and a shielding member that is made of a material having corrosion resistance against formic acid. The shielding member is arranged between a reflow processing section of the processing chamber and an inner wall of the processing chamber. In place of or in addition to the shielding member, the reflow apparatus may include a heater for decomposing residual formic acid.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Matsui, Hirohisa Matsuki, Koki Otake
  • Patent number: 8341468
    Abstract: A test unit is provided for executing a confirmation test on the storage area of the storage apparatus. A storage area management unit sets an accessible valid storage area in the storage area, and extends the accessible valid storage area to include a part of the storage area. The part of the storage area used to extend the accessible valid storage is confirmed for normal operation by the test unit.
    Type: Grant
    Filed: January 25, 2009
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Limited
    Inventor: Kunihito Onoue