Abstract: A rule learning method for making a computer perform rule learning processing in machine learning includes firstly calculating an evaluation value of respective features in a training example by using data and weights of the training examples; selecting a given number of features in descending order of the evaluation values; secondly calculating a confidence value for one of the given number of selected features; updating the weights of training example, by using the data and weights of the training examples, and the confidence value corresponding to the one feature; firstly repeating the updating for the remaining features of the given number of features; and secondly repeating, for a given number of times, the firstly calculating, the selecting, the secondly calculating, the updating, and the firstly repeating.

Abstract: A biometric information sensing apparatus, including a width detection device that detects a width of a biometric part in a biometric information image collected by a collection device that collects the biometric information image of the biometric part; a narrowing position detection device that detects a narrowing position of the biometric part in the biometric information image on the basis of the width; an orientation information obtainment device that obtains orientation information related to the biometric part in the biometric information image; and a determination device that determines a collection status of the biometric information image on the basis of the orientation information near the narrowing position.

Abstract: A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.

Abstract: A method of manufacturing a wiring substrate includes forming a conducting layer on a first insulating layer including a first glass cloth; forming a photosensitive resist layer on the conducting layer; recognizing a first origin position on the first insulating layer; forming a mask on the resist layer by positioning the mask with respect to the first origin position, the mask being formed so as to position wiring patterns only on positions overlapping the first glass cloth in a planar view; and exposing the resist layer via the mask and forming the wiring patterns only on the positions overlapping the first glass cloth in the planar view.

Abstract: When opposed communication transmitting apparatuses A and C are connected in a physical configuration thorough a communication transmitting apparatus B, if an interface configuration changing command is input to the communication transmitting apparatus B, the interface configuration is changed in the communication transmitting apparatus B and virtual connection is achieved such that the opposed communication transmitting apparatuses A and C pass through the communication transmitting apparatus B to directly connect an interface A1 and an interface C1. In this situation, since the GMPLS operation target apparatuses are only the communication transmitting apparatus A and the communication transmitting apparatus C and the communication transmitting apparatus B is a non-target apparatus of the GMPLS operation, the GMPLS scalability problem is solved and optical signals may be transferred at higher speed.

Abstract: A semiconductor integrated circuit including: a data input circuit inputting a data input signal from outside and outputting the signal; a comparison value register memorizing an expectation value of the output signal varying in accordance with an input to the data input circuit; and a comparing circuit comparing a value in accordance with a switching number of the output signal of the data input circuit and the expectation value, is provided.

Abstract: A method of fault notification in a communication apparatus, including terminating transmission of a signal over a transmission link; determining whether or not a specified fault notification signal is detected in a reception link and storing a determination result from the determining; and upon detection of a fault in the reception link after starting an operation, outputting a specified fault notification signal to the transmission link when the stored determination result is affirmative.

Abstract: A processing device which can execute a plurality of threads includes: an execution unit which executes a command; a supply unit which supplies a command to the execution unit; a buffer unit which holds the command supplied from the supply unit; and a control unit which manages the buffer unit. The buffer unit has a set of buffer elements. Each of the buffer elements has a data unit for storing a command and a pointer unit for defining a connection relationship between the buffer elements. The control unit has a thread allocation unit which allocates a sequence of buffer elements whose connection relationship has been defined by the pointer unit for respective threads executed by the processing device.

Abstract: A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit.

Abstract: An electronic apparatus includes: a housing having an internal space formed by top, bottom and side plates; and a power-source housing section formed next to a part of the side plate in the internal space and having a plate wall shaped such that a part adjacent to the side plate is near the side plate on one side and is away from the side plate on the other side in a direction connecting the top plate with the bottom plate. The apparatus further includes: a power-source block having an outer wall-surface whose shape conforms to the plate wall and housed in the power-source housing section; an antenna disposed in a space between the side plate and the plate wall; and a circuit board disposed in the internal space and mounted with an electronic circuit that operates based on power supplied from the power-source block housed in the power-source housing section.

Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.

Abstract: An interconnect board for interconnecting and arranged between a first circuit board and a second circuit board, the interconnect board includes a first conductive plate including a first connection terminal, a first insulating member wrapping the first conductive plate except for the first connection terminal, a second conductive plate including a second connection terminal, a second insulating member wrapping the second conductive plate except for the second connection terminal, an insulating substrate arranged between the first insulating member and the second insulating member, and a conductive member penetrating the first insulating member, the second insulating member and the insulating substrate.

Abstract: An information processing apparatus for speech recognition includes a first speech dataset storing speech data uttered by low recognition rate speakers; a second speech dataset storing speech data uttered by a plurality of speakers; a third speech dataset storing speech data to be mixed with the speech data of the second speech dataset; a similarity calculating part obtaining, for each piece of the speech data in the second speech dataset, a degree of similarity to a given average voice in the first speech dataset; a speech data selecting part recording the speech data, the degree of similarity of which is within a given selection range, as selected speech data in the third speech dataset; and an acoustic model generating part generating a first acoustic model using the speech data recorded in the second speech dataset and the third speech dataset.

Abstract: In a write operation, an error of regular data read from a regular memory cell is detected and corrected using parity data. A part of the corrected regular data is replaced with write data, to thereby generate new parity data. When write commands are supplied, the parity data starts to be read from a parity memory cell after the read of the regular data is started and while the regular data is read. Further, while the new parity data is supplied to the parity memory cell, the regular data starts to be read from the regular memory cell in response to a following write command. Accordingly, an access cycle time of a semiconductor memory can be reduced.

Abstract: An information recording/reproducing apparatus includes a registration unit that registers scheduling information to periodically record information; a recording unit that records the information on a recording medium based on the scheduling information; a reproduction unit that reproduces the information recorded on the recording medium; a deletion unit that deletes the information according to a deletion instruction from the recording medium; and an erasure unit that erases, when the number of times of reproducing the information according to the deletion instruction is zero, the scheduling information associated with the information from the registration unit.

Abstract: A capacitance sensor includes a first charging voltage detector configured to detect a change in a voltage loaded into a first capacitor between an electrode and a ground terminal a second charging voltage detector configured to detect a change in a voltage loaded into a second capacitor among a plurality of electrodes and a determiner configured to generate a determination signal based on a detection voltage transmitted from each of the first charging voltage detector and second charging voltage detector.

Abstract: An internal circuit has a plurality of circuit blocks operating by receiving an internal power supply voltage. An internal voltage control circuit generates a plurality of regulator control signals according to a combination of operating circuit blocks. A plurality of regulators operate in response to activation of the regulator control signals respectively to generate the internal power supply voltage by using an external power supply voltage. For example, as the number of the operating circuit blocks increases, the number of the operating regulators increases. By thus generating the regulator control signals according to the actual operation of the internal circuit to control the operations of the regulators, it is possible to reduce variation in the internal power supply voltage to a minimum. As a result, an operating margin of a semiconductor integrated circuit can be improved and a yield of the semiconductor integrated circuit can be improved.

Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

Abstract: A packet transmission apparatus includes: a plurality of communication ports; a switch for switching packets; a storage unit which stores a plurality of queues for respectively holding packets to be output from the plurality of communication ports; and a stop signal generating unit. The stop signal generating unit generates a stop signal for stopping packets directed to one of the communication ports from being input into the switch, if the amount of packets held in the queue for the one communication port is equal to or larger than a certain first threshold value, and if the sum of the amounts of packets held in the plurality of queues is equal to or larger than a certain second threshold value.

Abstract: According to an aspect of an embodiment, a high-speed operation method for directing a computer to process a coefficient matrix constituting simultaneous equations generated by modeling an analysis target into a mesh by using the finite element method and the boundary element method, said method includes obtaining two edges that are not on a same plane and that are the closest to each other from among edges defined in a mesh of a boundary modeled by the boundary element method, and ordering, in a vicinity of on-diagonal elements of the coefficient matrix, matrix elements in the coefficient matrix of simultaneous equations obtained for the two edges that are the closest to each other.