Abstract: Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.
Type:
Grant
Filed:
October 15, 2009
Date of Patent:
October 23, 2012
Assignee:
International Business Machines Corporation