Abstract: An apparatus is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer is placed directly on a heating surface to establish a high and uniform thermal gradient through the wafer. Heat in the wafer is removed from the other wafer surface. The apparatus for fabricating semiconductor devices utilizing temperature gradient zone melting comprises a base, heating means and heat sink means. Heating means comprises a platform having a generally planar heating surface adapted to receive the entire area of the one surface of at least one wafer. The heat sink means is spaced away from the other wafer surface to form a space therebetween, the space being adapted to receive a high heat conductive gas. The heat sink means and the gas cooperatively remove the heat in the wafer to enhance the establishment of the thermal gradient.

Abstract: Disclosed is a method of fabricating a semiconductor on insulator composite substrate comprised of a semiconductor layer adjacent an insulator substrate, the defect density profile of the semiconductor layer being low and relatively uniform, a relatively thin region of the semiconductor layer at the semiconductor/insulator interface having a substantially greater defect density. The method comprises the steps of depositing the semiconductor layer adjacent the insulator substrate, amorphizing a buried portion of the semiconductor layer without damaging the insulator substrate such as to release contaminants into the semiconductor layer, recrystallizing the amorphous portion of the semiconductor or layer, removing a portion of the semiconductor layer so as to expose the recrystallized layer, and depositing an additional semiconductor layer on the recrystallized layer to provide an essentially defect free semiconductor layer of any desired thickness.

Abstract: A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines.

Abstract: A semiconductive substrate, such as a silicon wafer, is mounted on a baseplate for inclusion in an optical device such as a liquid crystal light valve. An optical flat presses the top surface of silicon wafer toward the baseplate and against an O-ring seal surrounding a fluid adhesive. The fluid adhesive hydrostatically distributes the force of compression to guarantee optical flatness and self-compensation for the amount fluid adhesive surrounded by the O-ring. The optical flatness of the semiconductor substrate is limited only by the flatness of the optical flat against which it is compressed. Parallel alignment of the optical flat, the substrate and the baseplate is achieved by reflecting a laser beam through the semiconductive substrate and observing the interference fringes therein, while adjusting the relative alignment so as to maximize the distance between fringes.

Abstract: The present invention provides a circuit comprising (1) a logic element responsive to data of first and second negative voltage potentials, the logic element having a depletion mode MESFET data input gate, and (2) a depletion mode MESFET transmission gate operatively associated with the data input gate for enabling the selective serial transmission of data therethrough to the logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage of the data input gate being between approximately the first and second negative voltage potentials, the pinch-off threshold voltage of the transmission gate being between approximately the third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more

Abstract: Beam deflection apparatus 50 has first and second conductors 64 and 68 positioned transversely in the path of beam 67 and has a resistive connector 78 to be tuned to deflection amplifier 52 and transmission line 54 to provide magnetic deflection. Capacitive plates 74 and 76 are charged by the deflection current to provide substantially equal electrostatic deflection in the same direction.

Abstract: A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.

Abstract: A process is provided for forming the native oxide on a semiconductor surface comprising Hg.sub.1-x Cd.sub.x Te, where x ranges from 0 to 1. The process comprises exposing the semiconductor surfce to a mixture of ozone and oxygen containing an effective amount of ozone sufficient to form a native oxide thereon. The desired amount of ozone is conveniently obtained by passing oxygen from a source through an ozone generator provided with a source of high voltage.

Abstract: A device for illuminating a display surface. Light is introduced through an end surface of a transparent substrate having front and back plane parallel opposed surfaces and thereby directed into the interior of the substrate. The back surface is textured with a multiplicity of shallow depressions such as grooves or dimples which have shallow sloped sides. These sides are configured so that light is selectively directed from the interior of the substrate through a limited angle out of the substrate towards a display surface adjacent and coextensive with the back surface of the substrate and away from a viewer observing the display surface through the substrate. The device provides uniform, high contrast illumination of underlying large area graphic displays such as maps, photographs, charts, and the like.

Abstract: A power divider/combiner assembly is provided which matches the impedance seen at the input/output port with the impedance seen at the peripheral end of each of plural radial transmission lines. Impedance matching is accomplished through the use of an inverted microstrip on a substrate suspended over an air dielectric. The thickness of the air dielectric is varied along each transmission line in discrete steps from the common dividing/combining end to the peripheral end of each transmission line. The air dielectric thickness can be chosen independently for each section of line so that a characteristic impedance of from 40 ohms to greater than 130 ohms is achieved.

Abstract: A method and apparatus for improving the operation of infrared detectors of a type generally characterized by a semiconductive substrate of a first conductivity type which includes a detection region defined or bounded by a heavily doped backside electrode and buried layer of the first conductivity type. A charge coupled device (CCD) readout structure for transfers charge in an epitaxial layer of second conductivity type which overlies the substrate, and the detector further includes a heavily doped layer of the second conductivity type positioned between the epitaxial layer and the substrate to shield the charge carriers of the substrate from the CCD voltages. Means are provided by the present invention for the injection of minority charge carriers into the epitaxial region which are subsequently transferred to output means by the CCD.