Abstract: A signal comparison circuit is described which is implementable by a logic gate array structure without introducing the possibility of the large, incorrect error signals possible with phase comparators implemented by logic gate array structures. The circuit has particular applicability to phase-locked-loop circuits because it compares the frequency and phase of a first input signal with the frequency and phase of a second input signal in an error-free manner. A first master flip-flop triggered by the first input signal produces negative pulses, under the control of a NAND latch. A second master flip-flop is triggered by the second input signal to produce negative pulses, under control of the same NAND latch. The NAND latch is responsive to the outputs of the first and second master flip-flops. The first and second input signals are each delayed, and the delayed input signals are respectively used to trigger first and second slave flip-flops (which are slaves to the two master flip-flops).