Abstract: Cryptographic systems and methods are provided in which authentication operations, digital signature operations, and encryption operations may be performed. Authentication operations may be performed using authentication information. The authentication information may be constructed using a symmetric authentication key or a public/private pair of authentication keys. Users may digitally sign data using private signing keys. Corresponding public signing keys may be used to verify user signatures. Identity-based-encryption (IBE) arrangements may be used for encrypting messages using the identity of a recipient. IBE-encrypted messages may be decrypted using appropriate IBE private keys. A smart card, universal serial bus key, or other security device having a tamper-proof enclosure may use the authentication information to obtain secret key information. Information such as IBE private key information, private signature key information, and authentication information may be stored in the tamper-proof enclosure.

Abstract: Integrated circuits such as programmable logic devices are provided with hotsocket detection circuitry. The hotsocket detection circuitry monitors signals on data pins and power supply voltages. If the data pins become active before the power supply voltages have reached appropriate levels, a hotsocket condition is identified. When a hotsocket condition is identified, driver circuitry on the integrated circuit can be disabled by a hotsocket signal. Conductive paths may be used to share hotsocket detectors among multiple blocks of input-output circuitry.

Abstract: Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

Abstract: Programmable logic device power supply noise levels are characterized using internal measurements. By making power supply noise measurements internally, noise measurements are made without influence from device packaging or circuit board environmental effects. The input-output circuitry of a programmable logic device is configured to supply a power supply voltage from the output of an output buffer to one of the inputs of a differential input buffer. The other of the inputs of the differential input buffer is provided with a reference voltage from an external voltage reference circuit. The differential input buffer serves as a comparator and generates an output signal based on a comparison of the power supply voltage from the output buffer and the reference voltage. A noise monitoring circuit processes the output of the input buffer. The noise monitoring circuit may be based on a register.

Abstract: Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized data. A regular data port and priority data port may be provided so that priority data may be nested inside regular data during transmission. Various levels of data integrity protection may be provided. If no data integrity protection is desired, a user can opt to omit data integrity protection from a given integrated circuit design, thereby conserving resources. If data integrity protection is desired, the user can select from different available levels of data integrity protection. Data may be multiplexed using user-defined data channels.

Abstract: An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present.

Abstract: Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

Abstract: A universal patching machine is used to provide network-based security for a data network. The universal patching machine may be implemented on a network appliance located at the edge of the data network. From this location, the universal patching machine intercepts data traffic between the internet and the data network. The universal patching machine examines the intercepted data traffic to detect security vulnerabilities. If a vulnerability violation is detected, the universal patching machine modifies the data traffic to remove the violation. Fixing the data traffic in this way ensures that the vulnerability cannot be exploited in an attack against the data network. The universal patching machine is formed from patch processors and a packet controller. The patch processors are formed from network patches. In operation, the patch processors detect vulnerabilities and issue modification commands that direct the packet controller to fix the data traffic.

Abstract: A cable may be provided having a noise-suppression ferrite loaded magnetic tape wrapped in a spiral. The cable may have a strengthening cord at its core. Signal wires such as data wires and power wires may surround the strengthening cord. The signal wires may have copper cores that are coated with polytetrafluoroethylene insulating coatings. A metallized polyester tape may be wrapped around the signal wires to reduce electromagnetic interference. A braided copper shield may be formed over the metallized polyester tape. The magnetic tape may be wrapped around the metal braid. One or both edges of the magnetic tape may have uncovered areas in which no magnetic material is present. The cable may have connectors its ends. The magnetic tape wrap may extend from one connector to the other.

Abstract: Systems and methods are provided for performing static error analysis on source code. A computer system having an operating system may contain a number of source code files. During a normal build process, a build program may be used to set various compilation options and to invoke appropriate compilers that compile the source code files into executable code. Static analysis debugging tools may be used to perform static analysis on the source code files. The appropriate static analysis tools may be invoked using a static analysis tool management program. Directory, path and name modification may be used to invoke the analysis tools. A monitoring program may be used to determine how to invoke the tools. The operating system may be modified so that the static analysis tools are invoked in place of the compilers when the build program is run.

Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: A touch-down counter is provided that maintains a count of how many times integrated circuits are placed into contact with a contactor in a test handler. The test handler has a work press that places integrated circuits into contact with pogo pins in the contactor. The pins are subject to wear and should be maintained by periodic cleaning. The touch-down counter has a sensor such as a non-contact Hall effect sensor that is attached to the contactor. A magnet is affixed to the side of the work press. When the work press comes into the vicinity of the sensor, the sensor detects the presence of the magnet and registers a contactor touch-down event. A lifetime count of touch-down events may be displayed on the counter. When a recommended threshold value of touch-down events has been exceeded, a test system operator can remove the contactor from use for cleaning.

Abstract: Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data to produce output data. The output data may include information on an implementation of the circuit design in a given type of integrated circuit device and may include report data on how the implementation of the circuit design is expected to perform. An optimization assistance tool analyzes the design and constraint data and the report data to identify potential problem areas. Recommendations may be provided to the circuit designer on how to address potential problems. Selectable options are displayed for the circuit designer. By selecting an appropriate option, the circuit designer can automatically launch a tool to make recommended settings adjustments.

Abstract: Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable logic that is configured by a user. Depending on the type of user logic that is implemented by the user, the programmable logic device integrated circuit may have different timing needs for its memory blocks. The adjustable register and memory address decoder circuitry has associated programmable elements that are loaded with configuration data. The configuration data adjusts the timing characteristics of the adjustable register and memory address decoder circuitry to accommodate the user logic. The adjustable register and memory address decoder circuitry may be used to make setup and clock-to-output timing adjustments to optimize a logic design.

Abstract: Methods and apparatus for testing programmable integrated circuits are provided. Programmable integrated circuits include programmable elements that are loaded with configuration data to program programmable logic to perform a custom logic function. The programmable integrated circuits receive test configuration data from a tester to program the programmable logic into a test configuration. After the programmable integrated circuit has been placed into the test configuration by loading the test configuration data, test vectors are applied to the programmable integrated circuit to evaluate its performance. Test configuration data loading circuits are used in the programmable integrated circuits to control how the test configuration data is loaded into the programmable elements. When the adjustable circuits are placed in a low bandwidth configuration, relatively few input lines are used to load the test configuration data.

Abstract: The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.

Abstract: A current source is provided for use with integrated circuits such as programmable logic device integrated circuits. The current source has an operational amplifier with positive and negative inputs and an output. The output is connected to a common-source output stage. A current mirror circuit is connected between the common-source output stage and a positive power supply. An external circuit-board-mounted resistor and capacitor are connected in parallel between the common-source output stage and ground. The negative input of the operational amplifier receives a bandgap reference voltage. A feedback path is used to feed back a feedback signal from the output stage to the positive input of the operational amplifier. The feedback arrangement ensures that the bandgap reference voltage is applied across the external resistor, which, through operation of the common-source output stage and the current mirror circuit, establishes the magnitude of the current source output.

Abstract: An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associated features such as a weak pull-up feature, a voltage clamp diode feature, a bus hold feature, an open-drain feature, a differential input termination resistance feature, and a single-ended/differential mode selection feature. An input-output feature control register receives input-output circuit feature selection instructions. The feature selection instructions contain feature selection bits whose values determine which of the input-output circuit features are enabled in a set of input-output circuits for testing on the integrated circuit. The feature selection instructions can selectively enable one or more input-output circuit features in each input-output circuit.

Abstract: Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the lightly-doped base region, a low-resistance current path into the base region may be provided. The low-resistance current path may be provided by a base conductor formed from heavily-doped epitaxial crystalline semiconductor. Metal-oxide-semiconductor (MOS) transistors with narrow gates may be formed on the same substrate as bipolar transistors. The MOS gates may be formed using a self-aligned process in which a patterned gate conductor layer serves as both an implantation mask and as a gate conductor. A base masking layer that is separate from the patterned gate conductor layer may be used as an implantation mask for defining the lightly-doped base region.

Abstract: Integrated circuit varactors and methods for varactor fabrication are provided. Varactors are formed on integrated circuits that contain complementary metal-oxide-semiconductor (CMOS) transistors. The same semiconductor fabrication process steps are used to form both the varactors and CMOS transistors, thereby eliminating potentially cost-prohibitive changes to manufacturing process flows. Varactor performance is enhanced by including a deep n-well structure. The deep n-well reduces sheet resistance in the semiconductor portion of the varactor and improves the varactor's quality factor. The deep n-well is formed from the same deep n-well layer that is used to form the CMOS transistors on the integrated circuit. The varactor has two active electrodes. The electrodes are spaced farther apart than specified by semiconductor fabrication design rules. The number of contact vias used in one of the electrodes is less than the maximum specified by the design rules.