Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Abstract: A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

Abstract: A switching voltage regulator is stabilized against changes in input voltage by suppressing the increase in loop gain due to increased input voltage. The reduction of loop gain is achieved by use of a modified triangle waveform which is compared to an error signal to switch the regulator output stage.

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.