Abstract: A single communication stack may be utilized to setup a data transmission session between wireless devices. A primary physical layer corresponding to the single communication stack may be utilized by the wireless devices to perform discovery, pairing, and security setup operations when setting the data transmission session. A secondary physical layer may be utilized to perform high speed data transmission. The secondary physical layer may be integrated or managed via the single communication stack corresponding to the primary physical layer, and applications running on top of the single communication stack may utilize the secondary physical layer transparently. A portion of the transmitted data may be multiplexed onto other secondary physical layers that may be available to the wireless devices. Alternatively, transmission of data may comprise switching among available secondary physical layers.

Abstract: A method and apparatus for distributing video-on-demand loading include processing that begins by receiving a concurrent additional request for accessing a video program (i.e., while the server associated with the video program is processing one request for access to the video program another is received). The processing continues by providing the video program to a 2nd server in response to the concurrent additional request. The 2nd server causes the video program to be stored in the redundant array of independent disks (2nd RAID) associated with the 2nd server. The 2nd server processes the concurrent additional request via the 2nd RAID such that processing of multiple requests for the same video program is distributed throughout the video on demand system.

Abstract: A method for designing an integrated circuit having both fixed logic and programmable logic components. An intended set of applications for the integrated circuit is first identified. In addition, for each of the intended set of applications, the logic requirements are identified. An approximate number of configurable logic blocks and at least one fixed logic circuit are selected that, when combined to operate cooperatively, meet a substantial portion of the logic requirements and the logic functions of the intended set of applications. The method also involves designing the integrated circuit with the approximate number of configurable logic blocks arranged and interconnected to form a fabric that surrounds an opening, and inserting the at least one fixed logic circuit into the opening in the fabric. In addition, the method involves adding logic to the integrated circuit that interfaces the at least one fixed logic circuit to the fabric and input/output circuitry.

Abstract: A method and apparatus for multilevel signaling includes processing that begins by determining multilevel signaling operation conditions. The processing then continues by generating an adjust signal based on the determined multilevel signaling operation conditions. The adjust signal is used to change the magnitude of the multilevel signals produced via the multilevel encoding. The adjust signal may vary a supply voltage and/or vary gain of an amplifier stage.

Abstract: A tunable differential amplifier includes an amplifier circuit, a current mirror, a dynamic current regulator, and a dynamic output common mode regulator. The current mirror is operably coupled to the amplifier circuit and controls the current flowing through each leg of the amplifier circuit. The current through the current mirror is established based on a regulated current provided by the dynamic current regulator and a common mode error current signal provided by the dynamic output common mode regulator. The common mode error signal is representative of an error between the desired output common mode of the amplifier circuit and the actual common mode of the output of the amplifier circuit. The regulated current is based on the common mode of the input of the amplifier circuit. As such, the biasing current and the common mode output of the differential amplifier is dynamically regulated.

Abstract: A high-speed, low distortion line driver that includes an amplifying circuit and a differential input amplifier. The differential input amplifier includes a 1st amplifying transistor, a 2nd amplifying transistor, a 1st controlled current source, and a 2nd controlled current source. The 1st amplifying transistor is coupled in series with the 1st controlled current source and the 2nd amplifying transistor is coupled in series with the 2nd controlled current source. The 1st and 2nd amplifying transistors are operably coupled to receive a differential input signal and provide a gained and level shifted representation of the differential input signal based on the controlled currents provided by the 1st and 2nd current sources. The amount of gain is based on the transconductance properties of the 1st and 2nd amplifying transistors and of the 1st and 2nd current sources.