Abstract: A technique for logically connecting local area networks (LANs) that may be separated by wide area networks containing routers and other network components. A logical link is formed between two bridge-like devices called tunnelers, such that, once a tunnel has been established between two LANs, other devices on the LANs can communicate as if the tunnel were a bridge. The tunneling mechanism of the invention requires that each LAN or extended LAN have only one active tunneler at any particular time, referred to as the designated tunneler, and each of the tunnelers is configured to have knowledge of the identities of the other tunnelers. A tunnel is established after a successful exchange of messages between two tunnelers, and then traffic may be forwarded through the tunnel in a transparent manner. The tunneling mechanism permits messages to be forwarded between LANs separated by a wide area network containing routers.

Abstract: A browser for efficiently browsing large directory trees is presented. The browser uses authentication links as the structure through which the browser navigates. By adhering to the rules for a valid authentication chain, the browser increases efficiency by storing the results of preliminary steps to browsing.

Abstract: The problems of meeting tight latency requirement while keeping network design low in cost and complexity are solved by the present invention of a network controller with a transaction logic block and a descriptor memory. The invention allows the data buffers and the buffer descriptors to be located in two physically separate memory subsystems. Data buffers can reside in a main system memory which are shared by other system clients. The buffer descriptors, which typically require significantly less memory space than data buffers, can reside in a special dedicated memory which can be low cost. The invention provides a method to allow buffer descriptors to be located in a low latency memory, which can be local to the network adapter. The data buffers can be located in a system shared memory. This design allows system shared resources, e.g. main system memory or bus, to be designed with relatively longer delay budget.

Abstract: A computer program is executed in a forward direction to create a current state of registers and memory for the program. During the forward execution of the program, the pre-existing values of registers and memory changed by each instruction are recorded in a main log. During interactive debugging, reverse execution is simulated by displaying the contents of specified registers or memory locations. For each specified register or memory location, the main log is searched in a forward direction beginning at a specified time in the past and continuing until a value is found, or until the end of the main log is reached and a value is taken from the current state for the computer program. After simulated execution in reverse, the user may specify a changed value for a specified register or memory location, and then forward instruction interpretation is begun using the changed value, without changing the current state.

Abstract: A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels are allocated to different slices of memory, where `neighboring pixels` includes both consecutive pixels in a scan line, or pixels in consecutive scan lines. In addition, hardware is provided that allows for the individual memory slices to be independently accessed, thus allowed each slice to access data from a different 64 bit word in video memory during one video access period. Controllers which independently access the memory slices are advantageously totally time independent, to allow the most flexibility in the starting and finishing of the access of the memory slice. Performance is further gained by buffering of both the read and write requests to the video memory.

Abstract: A method implemented by a computer network adapter for automatic retransmission of any packet involved in an unsuccessful transmission attempt due to transmit buffer underflow conditions entails the steps of (a) stopping the transmission; and (b) retrying another transmission of the packet for up to a predetermined number of attempts with an increased transmit threshold. The transmit threshold is the number of bytes of data of the packet involved in the transmission that are stored in the transmit buffer prior to start of transmission. Preferably, for the initial transmission attempt, the adapter requires only a small number of bytes of the packet to be stored in the transmit buffer. After occurrence of a buffer underflow condition, the adapter attempts a retry in accordance with the algorithm only after a substantially larger portion of the packet has entered the transmit buffer for transmission. If any retry succeeds, the adapter need not issue an interrupt.

Abstract: A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.

Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits - gate arrays - it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data.

Abstract: The present invention includes an approach to index tree structure changes which provides high concurrency while being usable with many recovery schemes and with many varieties of index trees. The present invention permits multiple concurrent structure changes. In addition, all update activity and structure change activity above the data level executes in short independent atomic actions which do not impede normal database activity. Only data node splitting executes in the context of a database transaction. This feature makes the approach usable with the diverse recovery mechanisms, while only impacting concurrency in a modest way. Even this impact can be avoided by re-packaging the atomic actions, at the cost of requiring more from the recovery system.

Abstract: A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: A video subsystem of a computer processor is shown to include a graphics controller coupled to a video memory. A method for improving graphics performance for applications which use fewer bits per pixel than provided in the graphics subsystem includes the steps of rearranging the pixel and byte data in video memory such that corresponding bytes of different pixels are stored in different, simultaneously accessible locations of the video memory. With such an arrangement, accesses to video memory may be provided which utilize all of the available bytes of the video memory bus, thereby increasing the performance of the graphics operation. In addition, a graphics system having a plurality of independently operating memory controllers is shown to further improve graphics performance by ensuring that the video memory bus operates at full capacity.

Abstract: Disclosed is a containment system for shipping and handling probe card circuit boards. The containment system features a base member equipped with a recessed seating shelf for receiving and supporting the probe card, and a set of fasteners to hold the probe card securely in place. The base also has a second, upper-level, seating shelf to support a cover, and a second set of fasteners to hold the cover in position to seal the base and further secure the probe card in place.

Abstract: Method and apparatus for automatically closing gaps prior to painting a cel in a vector-based computer-aided drawing system. A drawing is processed, as it is entered by a user, to generate a stored planar map containing geometric and topological characteristics of the drawing. The planar map is searched to identify gaps and updated to store synthesized gap-closing vectors for those gaps smaller than a selectable size. The gaps are closed before the painting of the cel, or coloring of the drawing, so as to prevent unintended spill-over of the color into adjacent regions.

Abstract: An I/O bus into the cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus.

Abstract: A test system is provided which tests the on chip cache of a microprocessor (CPU). The test system provides test vectors to the CPU in a specified sequences. The CPU then uses its internal general purpose registers to write the vectors the cache memory locations. After writing, the data is read back and compared to an expected value. The results are then stored in other general purpose registers of the CPU. Using the CPUs general purpose registers to record the test results allows the test system to test many cache locations in parallel. Furthermore the test system allows the test to proceed in a fixed number of CPU clock cycles regardless of any detected errors.

Abstract: A system for interconnecting line cards attached to a networking hub is disclosed. The disclosed system operates by forming backplane networks between the line cards using shared data path resources within the hub. Each line card attached with the hub describes its hub internal networking characteristics and capabilities. A hub management agent obtains the specific capabilities and characteristics of each line card attached to the networking hub, from each of the line cards. The characteristics and capabilities of each line card include which of the shared data path resources are accessible to the line card, and how the line card is able to operate on those accessible shared data path resources. The capabilities and characteristics of the line cards are obtained by the management agent requesting each line card for the information. The request is initiated by a triggering event, for example power-up of the networking hub or attachment of a new line card to the networking hub.

Abstract: A computer implemented method for determining whether a first (S/R-Latch) description of a state element that is implemented as a set of interconnected electrical devices can be replaced by a second (D-Latch) description of the state element. The method includes the steps of providing a representation of the S/R-Latch description to the computer, causing the computer to apply to the representation a set of rules that define a relationship between the S/R-Latch description and the D-Latch description and that are independent of a topology of the set of interconnected devices, and causing the computer to replace the S/R-Latch description with the D-Latch description of the state element if the representation satisfies the rules.

Abstract: A forwarding information management system for a bridge or router is disclosed, including a method and apparatus for maintaining forwarding entries within a forwarding table. The forwarding table is allocated into forwarding entries, and the forwarding entries organized into forwarding entry sets. A set of free queues is used to manage the free space segments in the forwarding table that are not allocated into forwarding entries. Each free queue maintains pointers to free space segments of a particular size. A forwarding entry adding process creates a new forwarding entry set including a new forwarding entry, selects a non-empty free queue for free space segments large enough to hold the new forwarding entry set, and writes the new forwarding entry set one of the free space segments. Also included in the system are a forwarding entry deleting process, a learning process providing input for the forwarding entry adding process, and an aging process providing input for the forwarding entry deleting process.

Abstract: A system for controlling the transmission of cells from a network node over multiple virtual circuit is disclosed. The disclosed system performs traffic shaping for all virtual circuits connected with the network node. The system includes a virtual circuit table with one or more entries. Each virtual circuit table entry corresponds to a virtual circuit established with the network node. Each virtual circuit table further includes one or more Cell Rate Accumulator fields and a Time Stamp field. The system includes a schedule table having one or more entries. Each schedule table entry further includes one or more Cell Rate Accumulator fields and corresponding predetermined value fields. A schedule table loading process determines a virtual circuit on which a packet is to be transmitted, and then calculates a time elapsed since a last previous write of a virtual circuit table entry corresponding with that virtual circuit.