Abstract: A system and apparatus for generating an extended finite state machine (EFSM) from a specification expressed as a set of data relationships. The specification is written in a specification language designed for the purpose, and is parsed in a conventional fashion. The parsed specification is used as input to the method of the invention, which comprises routines for transforming it into an EFSM including states and transitions. The EFSM thus generated is used as input to a traversal procedure, for ultimately generating validation tests to verify the operation of an implementation of the specification, with one such test being generated for each path traversed through the EFSM. The traversal of the EFSM may be carried out in a conventional fashion or by using applicant's EFSM traversal method. The EFSM's transitions represent functions and test information, and the states represent the status of the EFSM at particular points, given the traversal of a particular path through the EFSM, i.e.

Abstract: An arrangement for mounting a heat sink to a mounting board. The arrangement includes a heat sink and a locking member. The heat sink has a bottom surface and a passageway extending therein from an entrance opening on the bottom surface in a direction normal thereto and terminating with a closed end at its inner end. The passageway has an entrance region tapering toward the closed end and an inner region defined by generally parallel side wall portions. The side wall portions defining the entrance region including an engagement surface facing the closed end of the passageway. The locking member is T-shaped with the member crossing the stem of the T adapted for snug fit engagement with the generally parallel walls of the passageway's inner region. Moreover, the crossing member has an engagement member at each of it's ends that extend toward the base of the stem. The engagement members interlock with the engagement surface when the locking member is inserted into the passageway of the heat sink.

Abstract: Transformers (T1, T2), switches (M1) and (M2), rectifiers (DR1, DR2, DR3, DR4) and low-pass filter (LF, CF) form a basic power train circuit (12). Auxiliary switches (A1, A2), diodes (DS1, DS2) and capacitors (CS1, CS2) form active clamp circuit (10). The capacitances for (CS1, CS2) are chosen large enough such that the voltages (vCS1, vCS2) across the capacitors are essentially constant during several switching cycles. Switches (M1) and (A1) are driven by the signal (V.sub.G1), while switches (M2) and (A2) are driven by (V.sub.G2). When (M1) is turned OFF, the energies stored in the magnetizing and leakage inductances in (T1) will resonate with the output capacitance of (M1) first. When the voltage (V.sub.M1) across (M1) exceeds the voltage (V.sub.CS1) across (CS1), (DS1) conducts and (V.sub.M1) is clamped at (V.sub. CS1), which has a steady-state value of slightly less than two times the input voltage (E). During this interval, the capacitor (CS1) is charged by the leakage inductor current (i.sub.LK1).

Abstract: A fixture (10) for bonding multiple components together includes a bottom plate (20), a middle plate (22) and a top plate (24). The plates (20), (22) and (24) are aligned by dowels (26) and clamps (30). Bottom plate (20) has a rectangular pocket (32) for holding heat sink (14) and alignment pins (34) for locating plastic pin grid array (PPGA) package (12) over the heat sink (14). An annular projection (40 ) covered with a conformal pad (42) extends from bottom surface (44) of the middle plate (22). Dowel (50) extends through openings (46) and (36) in the top and middle plates (24) and (22) to apply pressure to chip (16). A first spring (56) is mounted on the dowel (50) and compressed between the top plate (24) and a snap ring (58) to provide pressure from the dowel (50 ) on the chip (16). A second, larger diameter spring (60) is compressed between the middle plate (22) and the top plate (24) to provide pressure from the middle plate (22) on the PPGA (12).