Abstract: A method of erasing a memory block of a non-volatile memory, including setting a pulse width of erase pulses to an initial width, repeatedly applying erase pulses to the memory block until the memory block meets an erase metric or until a maximum number of erase pulses have been applied, gradually adjusting a pulse voltage magnitude of the erase pulses from an initial pulse voltage level to a maximum pulse voltage level, and reducing the width of the erase pulses to less than the initial width when the pulse voltage magnitude reaches an intermediate voltage level between the initial pulse voltage level and the maximum pulse voltage level. Thus, narrow pulses are applied at higher voltage levels to reduce the amount of over erasure of the memory block.

Abstract: A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit.

Abstract: A body control apparatus for an analog switch for minimizing leakage current and keeping PN junctions reverse-biased. The analog switch has first and second switch device clusters coupled between input and output nodes and controlled by a control input, each having a corresponding body junction. The body control apparatus includes body control devices each controlled by one of the input and output nodes for coupling a body junction to the opposite one of the input and output nodes. Each switch device cluster may include a main switch and body devices which keep the body junction of the main switch at a voltage level between the input and output nodes when the analog switch is on. When the analog switch is off, the body control apparatus activates when voltage across the input and output nodes rises to keep the body junctions at desired voltage levels.

Abstract: An LED driver with open loop dimming including a full wave rectifier circuit, a DC/DC converter, and an oscillator circuit. The rectifier is configured to receive an input voltage in the form of an AC conductive angle modulated voltage and to provide a rectified voltage. The DC/DC converter converts the rectified voltage to an output voltage and an output current, where the output current has a magnitude which varies proportionately with a square of a quadratic mean of the input voltage. The oscillator circuit controls switching of the DC/DC converter with constant frequency and constant duty cycle. The DC/DC converter may be a flyback converter and may include a transformer operated in DCM. The driver may include output voltage and/or output current limit. The output current may be limited when the input voltage is within normal operating range of an AC line voltage from which the input voltage is derived.

Abstract: An inrush current limiter for use with an LED driver including a current limiting device, a bypass switch device, and a switch drive. The current limiting device is placed in the input current path of the LED driver to limit input current to a predetermined maximum level in response to an AC conductive angle modulated voltage. The bypass switch device is coupled in parallel with the current limit device. The switch drive turns on the bypass switch device to at least partially bypass the current limiting device as a voltage level of an input of a switching converter rises. The input current remains sufficiently high without exceeding the maximum level. The switch drive is implemented with a delay network driven either by a separate transformer winding or by a snubber network. The delay network may have a delay based on the delay caused by the current limiting device.

Abstract: A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.

Abstract: An image processing system is disclosed which uses gain information from an input image to determine a threshold value used to filter the input image. The gain information is indicative of the amount of illumination of the input image and thus the noise level. The image processing system includes an image processor, a converter and a filter. The image processor receives and processes first image information into second image information and extracts the gain information from the first image information. The converter converts the gain information into a filter threshold, which is used by the filter to filter the second image information to provide filtered image information. The converter may include a lookup table storing noise characteristic estimates or the threshold values. The threshold values may further be based on subband size. The filter may be a wavelet-based transform denoising filter.

Abstract: A video adjustment system for processing video information is disclosed which includes a motion analyzer and an adjustment module. The motion analyzer determines a motion level metric of the video information based on at least one motion parameter. The adjustment adjusts an initial dynamic light scaling factor to provide an adjusted dynamic light scaling factor based on the motion level. The dynamic light scaling factor may be used for luminance compensation and backlight display scaling. The motion level may be based on any type of motion information, such as motion vector information or information indicating a scene change. A distortion module may perform a distortion evaluation of the video information for calculating the initial scaling factor. Alternatively, the distortion module may include a memory which stores predetermined scaling factors based on statistical distortion level characterization.

Abstract: A dyadic spatial down sampling filter having tap values configured according to a Kaiser window function a beta factor of approximately 2.5, having approximately 1.5 side lobes, and having a down sampling ratio of approximately 1.9. The dyadic spatial down sampling filter may have tap values [?1, 17, 32, 17, ?1]/64. A dyadic spatial up sampling filter having tap values configured according to a Kaiser window function having a beta factor of approximately 1.5, having approximately 2 side lobes, and having an up sampling ratio of approximately 2. The dyadic spatial up sampling filter may have tap values [?5.44, 0, 20.71, 33.46, 20.71, 0, ?5.44]/64.0, or tap values [?5, 0, 21, 32, 21, 0, ?5]/64, or tap values [?5, 21, 21, ?5]/32.

Abstract: A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage.

Abstract: A physical access control system is disclosed which includes a network, at least one access controller, a producer device, and a consumer device. Each access controller generates status and event information associated with a controlled physical barrier. The producer device includes producer logic which collects and stores the status and event information. The consumer device includes consumer logic which periodically polls the producer logic via the network to retrieve the status and event information from the producer device. The producer logic and the consumer logic communicate via the network according to a commonly accepted message syndication protocol, such as the RSS protocol or the Atom Publishing Protocol or the like. The use of a commonly accepted message syndication protocol simplifies communications, avoids proprietary configurations and facilitates integration, such as combining systems or adding new devices and the like.

Abstract: A method of simplifying deblock filtering of video blocks of an enhanced layer of scalable video information is disclosed which includes selecting an adjacent pair of video blocks, determining whether boundary strength of the video blocks is a first value, evaluating first conditions using component values of a first component line if the boundary strength is not the first value, and bypassing deblock filtering between the video blocks if the boundary strength is the first value or if any of the first conditions is false. The method may include bypassing evaluating conditions and deblock filtering associated with the maximum boundary strength. The method may include bypassing evaluating second conditions and bypassing corresponding deblock filtering if the intermediate edge is a horizontal edge. The method may include bypassing less efficient memory reads associated with component values used for evaluating the second conditions.

Abstract: An open loop modulation network for a voltage regulator including a latch network, an output sense network, a timing network, and pulse control logic. The latch network latches assertion of a pulse control signal and provides a corresponding latched control pulse indication. The output sense network detects initiation of an output pulse and provides a corresponding output pulse indication. The timing network initiates a delay period in response to the output pulse indication and resets the latched control pulse indication after expiration of the delay period. The pulse control logic terminates the output pulse after the latched control pulse indication is reset and the pulse control signal is negated, whichever occurs last. Very narrow input pulses are detected and either a minimum output pulse is generated or the output pulse is based on the pulse control signal.

Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

Abstract: A small computer architecture in which the CPU can receive multiple kinds of interrupt signals, including one kind which is assigned to indicate the occurrence of a keystroke input and another kind which is assigned to indicate the occurrence of a pointing device input. However, the computer does not include any pointing device as such. Instead, the keyboard microprocessor (i.e. a microprocessor other than the CPU) monitors user keystrokes to the computer's keyboard, and: in response to simple keystrokes, or keystroke combinations which include one of the basic chording keys, the keyboard microprocessor sends a keystroke interrupt to the CPU; and in response to keystroke combinations which include an additional chording key, the keyboard microprocessor sends a pointing-device interrupt to the CPU, and provides a data output corresponding to an emulated pointing-device movement.

Abstract: A computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.