Abstract: A method and apparatus for displaying a user selected region-of-interest clearly on a video display terminal in an audiovisual conferencing system is disclosed. The method comprising the steps of having a user select his or her region-of-interest on a display terminal with an input device, having the video decoder translate the user's selection to corresponding horizontal and vertical coordinates recognizable both by the video decoder and the video encoder, having the video decoder transmit the coordinates to the video encoder through a back transmission channel, and having the video encoder allocate bits originally for representing compressed video information outside the region-of-interest to represent compressed video information within the interested region of images and transmit the compressed video information to the video decoder through a forward transmission channel.

Abstract: A modular cooling apparatus for computer systems is disclosed. The apparatus includes an air-guiding duct, a fan coupling to the duct and a coupling apparatus for coupling the air-guiding duct and the fan to an electronics housing. The air-guiding duct has an input opening to the exterior of the electronics housing and guides ambient outside air to the input of the fan. Then the fan directs this outside air to the inside of the electronics housing. The electronic housing can be formed between a base module and the computer system circuit board or between the air-guiding duct, fan and a retention module. Furthermore, outside air is delivered in a substantially perpendicular direction relative to the plane of the computer system circuit board within the electronics housing.

Abstract: A method and apparatus for monitoring an output signal from and modifying an input signal to an audio/video system is disclosed. In one embodiment, the system response of said audio/video system is determined. After having established the system response, said input signal is modified according to said system response such that said output signal is a optimal reproduction of said input signal.

Abstract: A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

Abstract: An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the first input comprising a floating point number, the selector selecting zero to become the output when the floating point number is denormal and the mode bit is set, the selector selecting the floating point number to become the output otherwise.

Abstract: A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions, including macro branch instructions. The branch prediction unit is configured to receive the program instructions from the fetching unit, analyze the program instructions to identify the macro branch instructions, determine a first branch prediction for each of the macro branch instructions, and direct the fetching unit to retrieve the program instructions in an order corresponding to the first branch predictions.

Abstract: Each member system of a distributed collection of self-monitoring hardware systems includes receiving logic operative to receive a wellness token from a first other hardware system of the distributed collection of hardware systems. Each member system also includes modification logic, communicatively coupled to the receiving logic, operative to modify the wellness token to create a modified wellness token in a manner that reflects the wellness of the member hardware system, and transmitting logic, communicatively coupled to the modification logic, operative to transmit the modified wellness token to a second other hardware system of the distributed collection of hardware systems.

Abstract: Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit.

Abstract: An apparatus and a method for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity are described. In one embodiment, the apparatus includes a first phase-locked loop (PLL) coupled to a reference clock pin by a path of length L1 and a first PLL feedback pin by a path of length L2 such that L1.apprxeq.L2. In another embodiment, the apparatus includes a second PLL coupled to the reference clock pin by a path of length L3. The second PLL is coupled to an internal core of the integrated circuit by a path of length L4 such that L3.apprxeq.L4. In one embodiment, a computer system incorporating the apparatus includes a first propagation path of length L5 coupled to the first PLL output pin. The first PLL output pin is coupled to the first PLL feedback pin by a path of length L6 such that L5.apprxeq.L6.