Abstract: A radar jamming detection system is suitable for recognizing and distinguishing the presence of jamming and, particularly, terrain bounce jamming. The radar system includes a transmitter and a receiver. The receiver receives true radar skin return signals, in addition to ground clutter signals and jamming signals. The true radar skin return signals and ground clutter signals are recognizable in accordance with a predetermined receiver passband. Estimated target location, velocity and frequency data, as provided by a cueing radar, is used to set up the receiver passband for the radar detection system. Ground clutter range and angle measurements are used to determine an estimated ground range at the jammer angle, which is then compared with the cue range to determine if the received signals are terrain bounce jamming signals.

Abstract: A "navigation protocol" is implemented via a computer program to provide communication and invocation capability among object-oriented application programs and precompiled library routines, collectively referred to as `programs`. Each application program is "registered" with the operating environment during its installation; registration entails updating a registration-table data structure with information about 1) a program identifier; 2) an object-type identifier identifying a class of objects; and 3) an action identifier, e.g., a menu entry, identifying an action which the program can perform on objects of the class specified by the object-type identifier. A user can manipulate an object by selecting the object and requesting that a list of all actions performable on the object be displayed, then selecting one of the displayed possible actions.

Abstract: A bi-directional spatial power combiner grid amplifier has an array of parasitic elements between the lens and the amplifier. The elements have different impedances to radiation of a first polarization (incident radiation) and of a second polarization which is orthogonal to the first (amplified radiation), thereby providing impedance matching to both the input and the output of the grid amplifier. The elements preferably are separated slots or dipoles (some in each direction of polarization), crossed slots or dipoles, or micropatches.

Abstract: An opto-coupling device lies between an analog input circuit, such as a telephone line, and a processing apparatus, such as a modem. The device has a high impedance circuit; this is, its impedance is high with respect to the input impedance of the analog input circuit. This high impedance circuit has a voltage/current conversion circuit. The variations of the current flowing through the conversion circuit are directly induced by the variations in the voltage of the analog input signal. The high impedance circuit is in series with a constant current source, and is connected to the analog input circuit. The inputs of the opto-coupling device are in parallel with the voltage/current conversion circuit.

Abstract: A motor controller for control of an AC motor which monitors the DC power provided to an inverter for synthesizing AC waveforms having the needed frequency and phase to power the motor. Information about variations in the DC power to the inverter are incorporated into the control strategy by adjusting a motor base frequency at which the motor moves from a constant torque to a constant horsepower mode of control. The change of control mode allows decrease in the field current, and hence a decrease in the required quadrature voltage while preserving the torque current. The torque current is ultimately limited by a user programmable direct voltage limit.

Abstract: The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter 22. A narrow parameter from the CPU 10 produces a broad address for the generator 20 to pass to the memory 28. The converter 22 converts data between memory 28 format and CPU 10 format. A different context register 16 may be selected by each code line of software. The generator 20 preferably calculates a data element length which is the product of an odd number and a power of two, each number being specified in the content of the Context Register 16. Elements are clustered into groups, one group for each element length, and the groups are arranged in order of ascending element length. The index identifying the individual element of a group with a larger element length does not begin with zero (or one).

Abstract: An industrial controller I/O module includes on-board programming circuitry in the form of a microprocessor and associated memory, a first programmable logic circuit and a second programmable logic circuit connected through an isolation interface. The programmable logic circuits are programmed by the microprocessor on power up by reading configuration data from the PROM and writing it to the logic circuits to define their I/O circuit functions in controlling the I/O drives on a controlled machine or process.

Abstract: An improvement in rate-sensing tuning fork design includes a generally planar and H-shaped sensor frame of piezoelectric material. The frame includes a first pair of tines and a second pair of tines joined to an intermediate cross-piece. Connecting means is provided for connecting each of the second pair of tines to the other of said second pair at a location spaced from said intermediate cross-piece. The connecting means is preferably a connecting member formed of piezoelectric material, with the member being generally parallel to the intermediate cross-piece of the H-shaped frame and disposed between the second pair of tines. The connecting means prevents each of the tines of the second pair from vibrating directly toward or away from each other. A preferred method of use of the device is described.

Abstract: A phase only spatial light modulating device for variably changing the phase of light passing through the device without changing the polarization of the light. Two analog state ferroelectric liquid crystal phase only spatial light modulators are placed such that their smectic layers are orthogonal to each other. The angle of the molecules in the two modulators is controlled to be at the same angle. Whereby light passing through both of the modulators obtains a phase delay for arbitrary polarized input light without amplitude modulation or change in polarization state.

Abstract: An apparatus and method of accomplishing over-voltage protection for variable power levels and frequency applications including the microwave range. Clamping means are provided that instantaneously absorb over-voltage conditions for a brief period while simultaneously providing feedback control of a driver signal to reduce the source of the over-voltage condition.

Abstract: A bar code reader including automatic scan beam focusing based upon decoding performance is disclosed herein. The bar code reader includes a focusing lens which is movably supported along the light path of the scanning beam. An electric motor is coupled to the lens support to move the lens relative to the light beam source in response to control signals. The control signals are produced based upon the data error rate for the data produced by the decoding circuit of the reader from the signals produced by the photodetector therein. Based upon the data error rate, the electric motor is controlled to move the lens to focus the light beam and reduce or eliminate the data error.

Abstract: A method and/or apparatus used with a motor controller for finding RMS current and RMS terminal voltage in a three phase AC induction motor using electrical values known to the controller. An equation relates average current to RMS current as a function of the duration of a known non-conducting period. Another equation relates known voltages to RMS terminal voltage as a function of a known phase angle and the known duration of the non-conducting period in a supply line.

Abstract: The BRANCH DECISION ENCODING SCHEME shown herein overcomes the limitations of a dedicated debug port on a single chip computer processor. A dedicated debug port resolves many of the problems associated with an add-on logic analyzer, except for its limitation of an eight bit data interface. The 8 bit port is required as a trade-off between the device I/O requirements and development tools. During real time program development, it is virtually impossible to monitor the 24 bit program counter through a port only a third as wide. The present invention solves this problem by taking advantage of the sequential characteristics of application programs. There is a discontinuity in the program counter in only a limited number of situations: branches, jumps, subroutine calls and returns from subroutines, exceptions and returns from exceptions, traps and return from traps, and loopbacks to the tops of loops.

Abstract: The amplitude or frequency of a sinusoidal signal represented as sample values S.sub.1, S.sub.2, S.sub.3, S.sub.4 is estimated by computing a triplet of differences x.sub.1, x.sub.2, x.sub.3, where x.sub.1 is a difference between S.sub.2 and S.sub.1, x.sub.2 is a difference between S.sub.3 and S.sub.2, and x.sub.3 is a difference between S.sub.4 and S.sub.3. An indication of the estimate of the amplitude or frequency is computed as a ratio of algebraic functions of the differences x.sub.1, x.sub.2, x.sub.3. The amplitude is computed as the square root of a first ratio of algebraic functions, and the frequency is computed as an arc-cosine function of a second ratio of algebraic functions. Preferably the ratio is evaluated by a division operation computed as a polynomial approximation, and the square root function and the arc-cosine function are also computed as a polynomial approximation. Preferably ratios computed from a plurality of triplets are averaged together to give more accurate estimates.

Abstract: A circuit for detecting a system reset caused by the turning on of power supply of an electronic system. The circuit comprises: latch means coupled to said power supply having a SET input and an output, said output of said latch means being reset to a first predetermined state during power-on; feedback means for receiving said output from said latch means and said system reset, said feedback means activating its output when both of said first predetermined state from said latch means' output and said system reset are present; delay means coupled to the output from said feedback means and to said latch means, said delay means activating its output a predetermined time after said delay means receiving an activated output from said feedback means, said activated output from said delay means setting said latch means to a second predetermined state such that said feedback means remains de-activated when only said system reset is present without power-on.

Abstract: A single-precision multiplier used in a recursive digital filter is rendered more precise, without resorting to extended-precision or floating-point arithmetic. A double-precision multiplier produces a group of most significant bits (MSBs) and a group of least significant bits (LSBs). The LSBs are processed, including delaying them by one or two clock cycles, and are then added back to the LSBs produced during the present clock cycle. The top few bits of this first sum are right shifted as far as possible and added to the MSBs, the resulting second sum being the output of the overall multiplier.

Abstract: A modem is tested using HP3065 with AT commands. The modem is tested as a whole, thereby assuring that the correct components are being used and that they will work with one another.

Abstract: A method of shaping and polishing the surface of a polycrystalline diamond including the steps of diffusion smoothing the diamond surface with hot reactive metals, shaping the smoothed diamond surface by laser ablation using a pulsed laser beam, and ion-beam assisted polishing the ablated diamond surface to optical smoothness. The polished diamond can be used for high quality optics.

Abstract: A variable multi-threshold detection circuit for a sampled baseband signal in the receiver of a communication system using GMSK modulation is disclosed. The circuit comprises an integrate/dump circuit for accumulating a predetermined number of samples of the baseband signal to generate a sum for a present bit, a level selector for selecting a threshold from a plurality of groups of multi-thresholds based on an estimated phase offset and the binary value of two previous bits, a compare circuit for comparing the sum from the integrate/dump circuit with the threshold selected from the level selector to generate a binary value of either one of "0" or "1" for the present bit, and a delay circuit for delaying the present bit to be used by the level selector to determine a next threshold for a next bit.

Abstract: An apparatus and method for converting a charge packet into digital bit weights. The apparatus comprises a plurality of serially connected charge-coupled cells for receiving the charge packet at one end, such that the charge packet consecutively fills each CCD in the path. Also, a detector is coupled to another end of the CCD's for advancing charge within the CCD's and detecting whether each CCD is filled. A counter coupled to the detector for counting the number of CCD's which are not filled with charge, wherein the number represents a first form of digital bit weights of the charge packet.