Abstract: A dual register file MMX-type architecture comprises monitoring logic for identifying which registers in a register file have been written to. The monitoring logic is coupled to write-enable logic associated with each register. Detection logic indicates the occurrence of an instruction boundary event and asserts a signal indicating the possibility of data incoherence between the register files. Control logic coupled to the register files cause a transfer of data between the two register files in response to the asserted signal. The monitoring logic acts in conjunction with the write-enable logic to disable write operations to the receiving registers when the corresponding transferring registers have not been written to.

Abstract: A method and apparatus are provided for generating output pulses or oscillations in response to input analog waveforms which involves exciting, with a known but arbitrary analog waveform, a circuit with a variable operating point and having a transfer function characterized by an unstable operating region bounded by a first stable operating region and a second stable operating region. The analog waveform is characterized by having a first information region and a second information region. In response to sensing the first and second information regions, the operating point of the circuit is forced into its unstable and stable regions. This produces a sequence of oscillatory and non-oscillatory behavior at the circuit's output.

Abstract: A digital video effects system for producing live-action video effects in real time includes an address generator having a pair of 2-D tables for providing x-coordinate and y-coordinate offset values. A third 2-D table contains warp activation factors (activators) which are scaled by a clip and gain processing technique to produce scaled activators. The scaled activators are used to scale the x- and y-offset values which are then combined with the original raster-order addresses to produce frame buffer readout addresses. An output video signal is produced by an inverse mapping of the input frame buffer to the output. The 2-D tables provide control of the image on a pixel-by-pixel basis. The degree of scaling by the clip and gain unit varies with time so that the resulting readout addresses also vary with time. A video effect, therefore, is produced simply by adjusting the scaling of the clip and gain unit. Moreover, a variety of effects can be achieved simply by changing the various 2-D tables.

Abstract: A system and method for partial reconfiguration of a gate array includes generating a netlist by placement and routing of a logic circuit. The netlist is accessed to modify logic cells configurations created by the place and route operation. Based on the modifications, a partial configuration bitstream containing only bitstrings which implement the modified logic cells is created. The partial configuration bitstream is downloaded to the gate array, thereby effectuating a partial reconfiguration of the gate array. In an alternate embodiment, a system in accordance with the present invention includes software utilities which allow an application program executing in a system containing a programmable gate array to reconfigure the array on-the-fly. The utilities include routines for modifying the design in response to external conditions detected during run-time. This approach obviates the need for providing a set of predetermined alternate designs, allowing the application to make that determination on its own.

Abstract: A coupling member is disclosed for connecting together adjacent hanging file folders. An elongate member includes a slot is formed along the full length thereof and positioned to receive the upper edges of the leaves of two adjacent folders. In a preferred embodiment, the slot is defined by two spaced-apart surfaces which extend into the interior region of the elongate member. The interior region may be solid or may be partially or fully hollow. The elongate member has any one of a number of cross-sectional profiles, including semi-circular, rectilinear, triangular and concave shaped profiles. In another embodiment of the present invention, the coupling member includes two slots each for receiving one of two adjacent folders.

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

Abstract: A torsional sensing load cell comprises a load sensing member having first and second deflecting portions. Force-receiving areas are defined on upper and lower surfaces of the deflecting portions for bearing a load and its corresponding reactive force. This imposes a torque on the load sensing member which is detected by transducers positioned to detect torsional stress. The transducers are coupled in a bridge circuit and are placed such that the output signal of the circuit is insensitive to the location of an applied load.

Abstract: A memory device includes a memory cell whose data state is sensed by a sense amplifier. A balance amplifier having the same construction as the sense amplifier is utilized to sense a balance cell having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit is used to adjust the conductivity of the of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

Abstract: A modular electron beam device is disclosed, the device being housed in a modular enclosure containing a power supply subsystem coupled to provide power to an electron beam tube. The enclosure is shaped to permit stacking of plural such modular units in a way that the stripe-shaped beam emitted from each of the units completely irradiates a surface to be treated. Beams may lie on different lines but the combined beams sweep out a width on a surface which is a continuous span. In an alternate embodiment of the invention, the modular unit comprises a plurality of electron beam units, each comprising an electron tube and a filament and bias supply to power the tube. A single high voltage stack is common to the plural tube/filament/bias sub-units. A daisy-chain arrangement allows for the single high voltage stack to power all of the tube units. In yet another embodiment, the modular unit comprises a plurality of electron tubes powered by a single power supply.

Abstract: A method of training a recursive filter comprises updating recursive parameters of the filter with delta values computed from sampling of an error signal and obtaining derivative terms of the output signal with respect to the parameters. Adaptation using derivatives for FIR filters is known, but this technique was not available for IIR filters because of the unavailability of the derivative values. However, when it is realized that the derivative itself is recursive, a parameter derivative function is obtained which will produce derivative terms for updating the filter parameters with acceptable filter performance.

Abstract: A helical load cell includes a first pair of transducers disposed along a neutral axis of a helical coil. A second pair of transducers is disposed in diametrically opposed relation to the first pair. Sensitivity to side loading is eliminated by "splitting" the second pair of transducers. In another embodiment, each of the transducers in each pair are respectively oriented parallel and perpendicular to a neutral axis of the coil. This configuration provides a measure of torsional forces.

Abstract: An eight-bit RISC based microcontroller includes an eight-bit register file having a dedicated arithmetic logic unit (ALU), in addition to a general purpose eight-bit ALU. The register file further includes means for combining a pair of registers to provide a logical sixteen-bit register for indirect addressing. The dedicated ALU is a sixteen-bit ALU which provides certain arithmetic functions for the register pair, thus alleviating the computational burdens that would otherwise be imposed on the general purpose eight-bit ALU. A further feature of the invention is the inclusion of a paging register which is combined with the contents of the logical sixteen-bit register to provide an even greater addressing range. Yet another feature of the eight-bit microcontroller of the present invention is the means for directly reading and writing to any bit position within the register file with a single instruction.

Abstract: A digital signal processing system for executing instructions and processing data, including a program memory which stores the instructions and a first portion of the data, a data memory which stores a second portion of the data, and a program control unit connected to the program memory for receiving a sequence of the instructions and generating control signals for executing the instructions, wherein the program control unit is programmed to fetch at least one data value from the program memory in response to at least one of the instructions. Preferably, the system also includes a memory management unit connected to the program control unit and the data memory for generating address signals in response to at least one of the control signals for use in reading data values from the data memory.

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

Abstract: A lifting device that has a carriage supported by a chain which passes over a sprocket-wheel disposed to rotate about an axis and features a sensing device which allows detecting forces on the chain for a predetermined duration so that the weight of a load supported by the carriage may be determined by calculating an average weight during the duration. To further enhance the accuracy of the measurement, the load cell is designed to accurately measure the load placed thereon independent of the position of the load on the cell.

Abstract: A fixture for supporting printed circuit (PC) boards during wave soldering includes a rigid frame having a ledge formed along the inner perimeter of the frame. The ledge supports a PC board along a peripheral portion of the board. Channels are formed atop the frame for receiving slidably removable clamps. The fixture further includes a slidably removable rail coupled to the frame along its channels. The rail includes a ledge that is coplanar with the ledge of the frame. The rail can be adjusted to provide support for smaller PC boards. A drop-plate component includes a recessed area for receiving a PC board, and depressed regions for masking components on the board. Openings formed in the drop-plate expose desired areas of the board for soldering. The drop-plate, loaded with a PC board, fits into the frame along the ledges of the frame and/or the rail for a wave soldering operation.

Abstract: A radio frequency identification (RFID) tag includes a tank circuit for receiving a power signal transmitted on a radio frequency (RF) carrier by a remote interrogator unit. Information is conveyed from the tag to the interrogator by varying a resistive load placed across the tank circuit as a function of data read from memory. Corresponding variations in the reflected signals are then detected by the interrogator. An overvoltage circuit cooperates with a modulation circuit for providing transmission of data even during an overvoltage condition, thus avoiding masking of the signal under such conditions.

Abstract: An eight-bit RISC based microcontroller includes an eight-bit register file having a dedicated arithmetic logic unit (ALU), in addition to a general purpose eight-bit ALU. The register file further includes means for combining a pair of registers to provide a logical sixteen-bit register for indirect addressing. The dedicated ALU is a sixteen-bit ALU which provides certain arithmetic functions for the register pair, thus alleviating the computational burdens that would otherwise be imposed on the general purpose eight-bit ALU. A further feature of the invention is the inclusion of a paging register which is combined with the contents of the logical sixteen-bit register to provide an even greater addressing range. Yet another feature of the eight-bit microcontroller of the present invention is the means for directly reading and writing to any bit position within the register file with a single instruction.

Abstract: A chip package includes a circuit board having a first surface with an inner die-attach region, an outer signal trace region and an intermediate utility region. Within the utility region are a number of traces for providing fixed electrical potentials to an integrated circuit die mounted within the die-attach region. In the preferred embodiment, the utility region includes a ring-like ground trace, a V.sub.DD trace and a segmented outer trace, with the segments of the segmented trace being connected to at least two fixed voltages for operating the integrated circuit die. Bond wires or leads of a leadframe include inner wire/lead ends connected to input/output pads of the die and include outer wire/lead ends connected to either a trace or trace segment in the utility region or a signal trace located in the outer signal trace region. The resulting chip package may be of the ball grid array type.

Abstract: A programmable logic device in accordance with the present invention includes a partially populated switch matrix for coupling a plurality of logic blocks. Having a partial switch matrix reduces the silicon area requirement of the device. In addition, the capacitive loading is reduced, which improves propagation speed and lowers the power requirement of the sense amps, since smaller sense amps can be used. Bypass means are provided to allow the propagation bit lines (i.e. carry and shift lines) to bypass one or more logic block. Each of the logic blocks includes a plurality of logic cells. Means are provided among the logic cells to provide bypass capability for the propagation lines among the logic cells. The logic cells feature means for reverse propagation of the carry and shift bits among the logic cells. The logic cells of the present invention also feature reverse propagation with bypass.