Abstract: The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks, comparable to a domino structure. One key advantage of the domino ASA ADC is its modular structure; each block is independent from all others. The unity capacitors used need to be matched only within their specific blocks. The architecture is very flexible; it is possible to increase the resolution by adding more blocks of the same kind. The ASA ADC is very fast, its speed is only limited the RC constants during the sampling and measurement phase and the speed of the comparators used.

Abstract: A biasing circuit for a CMOS passive mixer core to stabilize its conversion gain, linearity and noise figure. The RF inputs are fed differentially from the two RF ports, the LO inputs are fed differentially from the two LO ports, and the IF outputs are obtained at the two IF ports. The biasing circuit comprises a reference current derived from the bandgap voltage and a n-channel MOSFET transistor. The conversion gain is stabilized by keeping the Vgs?Vth value of the passive mixer core almost constant at all process corners, temperature and power supply changes. This is achieved by implementing Vs in such a way that it will increase the same amount as VDD decreases, and that Vs will decrease the same amount as Vth increases.

Abstract: The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

Abstract: A method of forming a relaxed silicon-germanium layer for accommodation of an overlying silicon layer formed with tensile strain, has been developed. The method features growth of multiple composite layers on a semiconductor substrate, with each composite layer comprised of an underlying silicon-germanium-carbon layer and of an overlying silicon-germanium layer, followed by the growth of an overlying thicker silicon-germanium layer. A hydrogen anneal procedure performed after growth of the multiple composite layers and of the thicker silicon-germanium layer, results in a top composite layer now comprised with an overlying relaxed silicon-germanium layer, exhibiting a low dislocation density.

Abstract: A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of the memory sub array. Fewer MDQ sense amplifiers and fewer unique MDQ lines leads to a reduced chip layout area. The high address bit of the word line row address (RA) is used to select a particular main data sense amp by means of a control switch. Not only are the sense amplifiers multiplexed for the new sub array, but the data I/O are multiplexed as well, leading to a significant reduction in the number of circuits required.

Abstract: A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SIGN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/?5 Angstroms.

Abstract: Two embodiments of a GMR sensor of the bottom spin valve (BSV) spin filter spin valve (SFSV) type are provided together with methods for their fabrication. In each embodiment the sensor includes an in-situ naturally oxidized specularly reflecting layer (NOL) which is a more uniform and dense layer than such layers formed by high temperature annealing or reactive-ion etching. In one embodiment, the sensor has an ultra thin composite free layer and a high-conductance layer (HCL), providing high output and low coercivity. In a second embodiment, along with the same NOL, the sensor has a laminated free layer which includes a non-magnetic conductive layer, which also provides high output and low coercivity. The sensors are capable of reading densities exceeding 60 Gb/in2.

Abstract: A method of fabricating a current-perpendicular-to-plane (CPP) giant magnetoresistive (GMR) sensor stack, wherein the parasitic resistance of the high-resistance antiferromagnetic (AFM) pinning layer is effectively reduced by enlarging its surface area and forming between it and the remainder of the sensor stack an equal area, contiguous, thin, highly conductive ferromagnetic layer, the current channeling (CCL) layer. The magnetic properties and increased current carrying capacity of the CCL allows the AFM pinning layer to effectively couple to the pinned layer while eliminating the effect of its high resistance on the sensor sensitivity as measured by the GMR ratio, ?R/R.

Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

Abstract: Methods and systems to achieve linear and exponential control over a current to drive color LEDs have been achieved. Current digital-to-analog converters (IDAC) comprising each an exponential current digital-to analog converter and a linear IDAC, being cascaded to each other are used for a linear and an exponential control of a current driving a set of color LEDs, preferably RGB LEDs. The linear part of the IDAC, which is converting the mantissa of a floating-point number is used to control the color composition of the color LEDs. The exponential part of the IDAC, which is converting the exponent of the floating-point number is used to control the brightness of the color LEDs. While fading from one color to a next color a linear color change is required. The exponential part of the IDAC is used to dim the LEDs from bright to dark and vice versa. In order to get the visual perception of a linear dimming an exponential current change is required.

Abstract: An apparatus, a method and a program are provided, each of which is intended to produce small prints. A variety of graphics are useful as framing elements for outer framing and tabulation with no need for increasing the volume of information to be prestored. One optional character, e.g., a pictogram, can be designated as a front ruling element and/or a rear ruling element for outer framing and tabulation. The optional character is chosen from among characters capable of input as character elements in lines of input characters. Upon execution of a print command, dot development is performed with respect to the front ruling portion and/or the rear ruling portion by utilizing fonts as character elements. Line types for upper ruling and lower ruling can also be designated, thereby effecting dot development depending upon the designated types of lines.

Abstract: An MRAM array is formed of MTJ cells shaped so as to have their narrowest dimension at the middle of the cell. A preferred embodiment forms the cell into the shape of a kidney or a peanut. Such a shape provides each cell with an artificial nucleation site at the narrowest dimension, where an applied switching field can switch the magnetization of the cell in manner that is both efficient and uniform manner across the array.

Abstract: Both the sensitivity and the reproducibility of processes for measuring low density ion implant doses near a semiconductor surface have been improved by first forming a thermal oxide layer on the surface and then adjusting the implant profile so that it peaks at the semiconductor-oxide interface. Additionally, variations in the initial wafer surface condition have been minimized by controlling the charging dose and sequence prior to performing the measurements.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: A battery charging, discharging, and protection switch circuit with enhanced reverse voltage protection is achieved. The circuit comprises, first, field effect transistor (FET) switches having gate, source, drain, and bulk. The FET switches may comprise either NMOS devices or PMOS devices. Second, means of controlling the FET switch's gate and bulk are included. The FET switch gate voltage determines the OFF and ON state of said FET switches. The bulk is switchable coupled between the battery terminal and the load terminal. To achieve high voltage breakdown limits the FET switch is realized with cascaded MOSFETs, where as a novelty here under certain operating conditions, i.e. the battery charger coupled in reverse condition—one FET is working as a source follower. All the necessary MOSFET switches are integrated onto a single chip, together with its controller logic. To form these MOSFETs within a single IC together with the other circuit elements is much less expensive.

Abstract: A method and circuits to improve the stability of low dropout voltage regulators having an adaptive biased driving stage. Said improvement of stabilization is valid through the total range of output current possible. A serial impedance is added to the gate capacitance of the PMOS pass device of said LDO. Said serial impedance could be a resistor or a transistor. In case of low load currents said impedance is not dominating, for high load currents said impedance keeps the gate pole close to the resonance frequency of the output tank. In case of medium load currents, wherein the inner resistance of the driving stage is about equal to said serial impedance, the gate pole could get too low. This problem is solved by reducing said serial impedance by shunting. Said shunting can be performed stepwise depending on the size of the load current.

Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.