Abstract: A method and apparatus for efficiently representing, maintaining and managing a project and enclosed lifecycles in a data processing system used to support a people-oriented work environment. An object-oriented language environment is utilized to represent projects, processes, states, transitions, users, roles, authorities, actors, members and activities as objects. Process, member, and authority objects inherit from project objects. State objects inherit from process objects. Transition objects inherit from state objects. Project and user objects inherit from actor objects.

Abstract: Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

Abstract: A system and method of using spare disk bandwidth and buffer capacity maximizes the system throughput of a multimedia server. An important issue is determining a criterion for selecting a data stream for which the additional disk bandwidth should be used. Minimization of buffer consumption is selected as the criterion to select an appropriate media stream to use the spare system resources. Buffer consumption measures not only the amount of buffer but also the amount of time the space is occupied (i.e., the space-time product). Even though both currently active streams and waiting streams can be chosen to adjust the rate of retrieval, it is generally more effective for the active streams.

Abstract: A method and apparatus for looking up source matches in a central processing unit (CPU) is utilized to identify dependencies between instructions that have been renamed via buffer renaming techniques. In such instances, when a particular instruction's source is a previous instruction's destination, that match needs to be identified such that dependent relationships between instructions are maintained. The source lookup method and apparatus utilize an allocation pointer and deallocation pointer, which point to the rename buffer, to produce a comparison window. For a given source of a given instruction, the comparison window is used to compare whether the source in question has a match within the rename buffer. If only one match is found, that rename buffer location is flagged to indicate that this particular location has a dependent relationship with the current source in question. If more than one match has been identified, a selection is made to choose the buffer location closest to the allocation pointer.

Abstract: A schematic modifier editor that works in concert with a shapes modifier editor so that changes to a design layout are reflected in the schematic. The shapes modifier editor tracks the changes made to the cell hierarchy and saves the changes to a list file. The schematic modifier editor processes the list file and edits the schematic file so that its cell hierarchy corresponds with that of the modified shapes file. The modified schematic file and modified shapes file can then be compared by a conventional verification program to ensure that the modified shapes file implements the desired circuit.

Abstract: An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to a I/O bus, an address management unit, connected to the processor address bus, to the memory system, to an I/O bus, and to a system initialization storage device, storing an initialization routine and data, wherein system initialization includes, in response to an Initial Program Load Read command issued by a processor, the steps of returning initialization data to the processor if the IPL read is accepted (IPL data available) by a device attached to the processor bus; if no device attached to the processor bus responds with IPL data, passing the read IPL command to the I/O bus under control of the data management unit; if the read command is accepted by an I/O controller attached to the I/O bus, returning initialization data to the processor; if no I/O controller accepts the IPL read command, passing the read command to the system initialization storage

Abstract: A distributed information handling system includes one or more processing units, a memory system including one or more memory modules, one or more routers, one or more terminal devices an N port switch which connects selected processing units to selected memory modules and to the terminal devices through the one or more routers, where device configuration is controlled by a configuration routine running in a primary processing unit, and which configures all configurable devices in the system in a tree structured manner, each device being configured with respect to a nearest neighbor in the tree.

Abstract: An information handling system includes a system memory controller having a control register in which a bit is reserved for Doze mode control. The Doze control bit is set by system software whenever it places any processor into Doze mode. Until this bit is set, there is no wake up signal issued nor any performance lost. Whenever this control bit is set, the memory controller sends a signal to the system arbiter that informs it to issue a "wake up signal" before issuing an address bus grant, in time to satisfy the processor wake up latency. In addition, if the system arbiter receives another address bus request within a predefined time window, the "wake up signal" is held active without adding to the bus grant latency. If maximum system performance is desired (all processors out of Doze mode), the system software resets the Doze mode control bit in the memory controller, which removes the signal to the system arbiter which controls the wake up signal and removes the added latency for granting the bus.

Abstract: This invention describes a computer application system and method for automatically deriving data mappings by processing stored data mappings. Derived data mappings are system generated data mappings. The system comprises a plurality of stored data mappings, a data mapping report generator, and a data mapping tool. Heretofore, data mappings were created by human analysis of data from two or more sources to determine the relationship between data fields. This time consuming process has been eliminated by the present invention. The derived data mappings may be stored for later use or provided to other system programs. The derivation may be performed at various levels of abstraction. Derived data mappings that should not be used are also identified.

Abstract: A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

Abstract: Lazy loading of executable library objects reduces operating system overhead and memory commitment requirements by postponing object loading until object references are expected. Initial task loading allocates only the main executable and library objects referenced by that executable. Secondary referenced objects are not allocated. Object references cause page faults for allocated but not loaded pages. Page fault handling causes loading and fixup of executable objects. Page fault handling also determines the next level of object references and allocates memory for the next object level. Shared memory systems allow sharing of executable objects until explicitly referenced. Once referenced, memory fault causes copying and fixup to referencing task memory area.

Abstract: A method for testing programming interfaces including application program interfaces and command line utilities. Each interface may be called from a loop instruction in a test instruction a number of times corresponding to a number of parameter sets which are needed to test each interface. The parameter sets are maintained in a separate data file and are retrieved for each call being made to an interface. One or more return value are included in the parameter set. The operating system generates one or more return values which are compared with the stored return value. A judgment is made based on the comparison of the stored return values and the programming interface-generated return value. When this comparison is not as expected, the return values are written to a file along with the parameter set which produced the unexpected comparison.

Abstract: Regulation of the output voltage of a power supply employing a flyback-type self-oscillating DC-DC converter employing a transformer. The primary winding circuit of the transformer senses a current recirculation loop for discharging the energy cyclically stored in an auxiliary winding of the self-oscillation loop of the converter such as to represent a replica of the circuit of the secondary winding of the transformer and by summing a signal representative of the level of the energy stored in the auxiliary winding with a drive signal on a control node of a driver of the power switch of the converter.

Abstract: An information handling system includes one or more processing units, a data bus management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, to the I/O bus, and one or more I/O controllers, where the address and data management units isolate the processor buses from the I/O bus and the memory system.

Abstract: A data processing system gives an application running on the operating system exclusive ownership of a hardware device. The system is operable in two modes. In the first mode the application interacts with the hardware device by making use of the processing system. In this mode many layers of the processing system are involved and the interaction time with the hardware is slow and inconsistent. In the second mode, exclusive ownership of the hardware device is granted to the application by the driver. In this mode the application has direct access to the hardware device thus avoiding the involvement of the processing system layers. The application accesses and uses the driver through a low latency processor interface linked into the application program itself.