Abstract: A computer system that has a main memory and a writeback cache memory also has an I/O device capable of data streaming. A memory controller responds to signals that the I/O device will perform a burst transfer of data to the main memory and blocks potential writebacks from the cache memory to the I/O device. Potential writing over of the data from the I/O device by a flushed cache line written back to the main memory is thereby prevented. The system performance is increased since the data from the I/O device can be written to the main memory without waiting for a snoop cycle and a writeback to be performed.