Patents Represented by Attorney, Agent or Law Firm George H. Gates
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Patent number: 5668995Abstract: A computer-implemented capacity planning system for multiprocessor computer systems used in client/server environments. The capacity planning system provides a correctly sized and configured computer system in response to user specified requirements. The user specified requirements comprise workload parameters. The generated output from the capacity planning generally comprises a recommended multiprocessor computer system, the number of processors needed in the system, the amount of memory required, and the configuration of a disk subsystem suitable for the system, including the number of disk drives, the size of each of the disk drives, and how they should be configured for best performance. The generated output from the capacity planning system further comprises a list price, discounted price, maintenance costs and price/performance indicator for the identified computer system configuration.Type: GrantFiled: April 22, 1994Date of Patent: September 16, 1997Assignee: NCR CorporationInventor: Kabekode V. Bhat
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Patent number: 5655086Abstract: A computer-implemented "Quality Information Products Process-Performance Support System" (QIPP-PSS) assists a user through the process of developing a training course or documentation. The QIPP-PSS typically operates on a computer having a monitor and a memory for storing electronic records related to the organization of projects. Each project is divided into one or more phases, each phase is divided into one or more work activities, and each work activity is divided into one or more job aids. The records for the projects, phases, work activities, and job aids include linkages to maintain these relationships. The job aids may comprise a boilerplate file providing templates for a project, a help file explaining how to use the template, linkages to a reference guide explaining the job aid, examples providing models of completed work activities, and project forms for documenting work in progress using the templates from the boilerplate file.Type: GrantFiled: April 28, 1994Date of Patent: August 5, 1997Assignee: NCR CorporationInventors: Thomas W. Jury, Kent L. Gustafson, Thomas C. Reeves, Kevin C. Cole, George Huffman
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Patent number: 5642363Abstract: A testing method and apparatus for testing complex board assemblies by configuring the data paths on the multiple boards into one larger virtual data path. The system uses reconfiguration commands and serial data streams to test the virtual data path, and reconfigures the virtual data path as sections are tested to shorten the virtual data path after each data stream is verified, thereby reducing test time and cost.Type: GrantFiled: December 21, 1995Date of Patent: June 24, 1997Assignee: NCR CorporationInventor: Gregory James Smith
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Patent number: 5640536Abstract: An architecture and method for operating a work station. The work station includes a CPU, a bus interface unit and a control line. The CPU is selected from a group of CPUs differing in certain operational parameters. The bus interface circuit is connected between an external bus and the CPU. The control line is connected to the interface circuit and provides a signal indicating the type of CPU connected to the circuit.Type: GrantFiled: August 30, 1991Date of Patent: June 17, 1997Assignee: NCR CorporationInventors: Edward C. King, Anton Goeppel
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Patent number: 5640584Abstract: A virtual processor method and apparatus for parallel computer systems that increases the level of parallelism to include multiple threads per node. If a processor node has a plurality of storage devices attached, a single thread can be allocated to each device. Similarly, if a processor node has multiple CPUs, each individual thread can utilize a different CPU. Thus, a task could potentially occupy all available hardware in the system. The result is increased system utilization and availability.Type: GrantFiled: December 12, 1994Date of Patent: June 17, 1997Assignee: NCR CorporationInventors: David R. Kandasamy, John R. Catozzi, Douglas W. Heying
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Patent number: 5608426Abstract: A method and apparatus for managing palettes in collaborative systems. This includes one or more host computers connected to one or more remote computers, wherein an image displayed on the host computer is substantially simultaneously displayed on the remote computer. The invention recognizes when a change is made to a system palette on the host computer, and communicates those changes to the remote computer. A logical palette is created on the remote computer to reflect the system palette on the host computer, and the changes made therein. A system palette on the remote computer may be updated to reflect the logical palette, and the changes made therein, depending upon whether the collaborative system is active or idle. When sharing images between the host computer and the remote computer, the images must first be translated from their device dependent format using the system palette on the host computer into a device independent image.Type: GrantFiled: September 28, 1993Date of Patent: March 4, 1997Assignee: NCR CorporationInventor: John Hester
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Patent number: 5579529Abstract: A method for the configuration of peripheral adapters in computer systems. The method examines a flag in a Configuration Space of the peripheral adapter to determine if user-selectable configuration options are required for the peripheral adapter. If the flag is set, then a configuration file is retrieved and interpreted to determine how the peripheral adapter should be configured and to determine how the configuration options should be presented to the user. Such configurations options may be conditional and based on previous user selections. Once the user's selections have been made, the method updates registers in the peripheral adapter with the selected option values.Type: GrantFiled: April 19, 1995Date of Patent: November 26, 1996Assignee: NCR CorporationInventors: Michael R. Terrell, Jeffery W. Kaisner, Jonathan D. Amsden, Thomas C. Burke, David K. Todd
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Patent number: 5563633Abstract: The present invention discloses a method and apparatus for performing data compression during monitor refresh operations. In one embodiment, it is envisioned that the compression functions would be performed in a refresh compaction device and the de-compression functions would be performed in a RAMDAC, thereby requiring only the transfer of compressed data between the refresh compaction device and the RAMDAC. In an alternative embodiment, it is envisioned that both the compression and de-compression functions would be performed in the refresh compaction device. Regardless of implementation, a "critical fill" level is determined during compression and a "critical fill" interrupt is generated during de-compression to gain control of the frame buffer before the compressed digital data is fully depleted.Type: GrantFiled: December 30, 1993Date of Patent: October 8, 1996Assignee: AT&T Global Information Solutions CompanyInventor: Donald H. Parsons
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Patent number: 5550981Abstract: A method and apparatus for binding network identities to locally-meaningful identities in a computer network is disclosed. A client computer is connected to a server computer that performs various functions requested by an operator of the client computer. The server computer assigns a temporary locally-meaningful identity to the operator of the client computer, and receives and responds to requests to perform functions from the client computer. The server computer triggers an ownership fault in response to a particular request received from the client computer. The particular request that triggers the ownership fault may be a request to create a file, a request to create a directory, a request to take ownership of an existing file, a request to take ownership of an existing directory, or other function.Type: GrantFiled: June 21, 1994Date of Patent: August 27, 1996Assignee: AT&T Global Information Solutions CompanyInventors: Eric Bauer, Russel W. Schaffer
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Patent number: 5507002Abstract: A Peripheral Component Interconnect (PCI) bus provides component level interconnection of processors, peripherals and memories. A bus protocol mechanism includes a Special Cycle command for defining "soft", i.e., configurable, transaction types for use between devices communicating on the PCI bus. Using the Special Cycle command, two or more devices attached to the bus can establish a device-specific logical signalling channel that expands upon, but does not violate, the PCI specification. This device-specific signalling channel provides logical sideband signaling between PCI bus devices, when such signaling does not require the precise timing or synchronization of physical signals. This allows the systems designer to define necessary sideband signalling without requiring any additional pins on the PCI bus.Type: GrantFiled: December 24, 1992Date of Patent: April 9, 1996Assignee: AT&T Global Information Solutions CompanyInventor: Thomas F. Heil
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Patent number: 5502824Abstract: A Peripheral Component Interconnect (PCI) bus has a protocol that guarantees that at all times, except for turn-around clocks necessary to prevent contention, that the bus is actively driven to a logic 1 or 0 by some device attached thereto. As long as all devices attached to the bus are compliant with the specification, the bus will never be left floating for long intervals, and thus the system designer is free to eliminate the pull-up resistors typically required on other buses.Type: GrantFiled: December 28, 1992Date of Patent: March 26, 1996Assignee: NCR CorporationInventor: Thomas F. Heil
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Patent number: 5392407Abstract: A dual-port processor architecture wherein a first port interfaces to a PCI bus and a second port interfaces to a RAMBUS channel.Type: GrantFiled: December 24, 1992Date of Patent: February 21, 1995Assignee: NCR CorporationInventors: Thomas F. Heil, Craig A. Walrath, Jeff A. Hawkey, Jim D. Pike