Abstract: In the present invention a voice and data network is disclosed that has applicability to a home or building where existing phone lines are used to interconnect multiple phones and computers within the network. Voice and data modules connect telephones and computers to the existing telephone wiring in a home or building. A link to wide area network allows phone calls to be placed between the network and the Public Service telephone network. All devices connected to the telephone wiring have their own ID and communicate by Tokens in Ethernet technology. This allows Ethernet packets to perform a plurality of communications between a plurality of devices connected to the network under the control of tokens. The communications is accomplished by passing packets containing voice and data signals between phones and computers internal to the network and to an external port to connect to outside of the network.

Abstract: A method and device to synchronize sampled digital data transferred from an input section to an output section prevents data overrun or underrun due to timing differences of timing signals of the input and output section. The timing synchronization device has an input sampled data counter to determine a number of samples in a frame time of the input sampled data. The timing synchronization device further has an interpolator to estimate data sample values for each sample of the input sampled data to coincide with each sample of the output sampled data if the number of samples in said input sampled data is less than an expected number of samples in said output sampled data.

Abstract: This invention describes an apparatus and method for the fast and efficient generation of addresses for a circular buffer involving only addition. The invention uses as input the present address, the base address, the length of the circular buffer and the address offset to the next address. The address offset can be either a positive or negative value, and the polarity of the offset is used to control different operations within the apparatus. The apparatus is constructed of two adders, a comparator and a multiplexer, and the next address is selected from the output of either of the two adders based on the output of the comparator.

Abstract: A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well.