Abstract: A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate.

Abstract: Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD.

Abstract: A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.

Abstract: A process is provided for making semiconductor structures, such as CMOS structures, which includes forming on a surface of a semiconductor body a layer from a material which is impervious to oxygen diffusion therethrough and patterning this layer to define the position of both the active and field isolation regions by partially removing this layer from the areas where the field isolation regions are to be formed. This oxygen impervious layer may be a dual dielectric structure consisting of a layer of silicon dioxide adjoining the semiconductor body and a layer of silicon nitride adjoining the silicon dioxide. The resulting structure includes an oxygen impervious layer which is used both for protecting all underlying oxidizing regions from oxidation and for defining the position of the active regions of the structure.

Abstract: The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.

Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.

Abstract: A method for diffusing a conductively determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a layer of a rare earth boride material over a predetermined surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the boride material to diffuse into the adjoining portion of the substrate to modify its conductive characteristics. At the same time a good electrical ohmic contact is established between the boride material and the adjoining substrate portion while the boride material retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.

Abstract: A method for diffusing a conductivity determining impurity in a semiconductor substrate and making electrical contact thereto by depositing a conductive layer made of a rare earth hexaboride material containing a predetermined amount of silicon in it over a surface portion of the substrate and heating the substrate for a predetermined period of time at a predetermined temperature which is sufficient to cause boron from the hexaboride material to diffuse into the adjoining portion of the substrate to modify its conductor characteristics. At the same time a good electrical ohmic contact is established between the conductive layer and the adjoining substrate portion while the conductive layer retains its conductivity even after the outdiffusion of some of its boron into the substrate during the heat treatment.

Abstract: An improved method for making polycide structures for use in electrode and wiring interconnection applications. It includes depositing a layer of polysilicon on an insulating layer and forming on this polysilicon layer a silicide structure and a silicon capping layer. The deposited layers are defined and etched through dry etching techniques using a dry etching mask made of a refractory metal that does not form a volatile halide in a dry etching environment. Metals with such characteristics include cobalt (Co), nickel (Ni), iron (Fe), and manganese (Mn). The metal mask and the other deposited layers may be formed and defined using a photoresist mask as a deposition mask formed to be compatible with lift-off techniques.The silicide may be deposited either through a chemical vapor deposition process or through evaporation techniques. If it is formed through the co-evaporation of metal and silicon, then the structure is subjected to a low temperature reaction annealing step at a temperature between 500.degree.

Abstract: An improved method of fabricating a stable high dielectric constant and low leakage dielectric material which includes oxidizing at a temperature of about 600.degree. C. or higher a layer of a mixture of a transition metal nitride and silicon nitride to produce a mixture which includes an oxide of the transition metal and silicon nitride. The initial mixture of transition metal nitride and silicon nitride may be deposited by reactive sputtering techniques or other known deposition techniques on, a semiconductor or an electrically conductive layer, and the thickness of the mixture should be within the range of 3 to 50 nanometers. By depositing an electrically conductive layer on the oxidized mixture, a capacitor having a high dielectric, and low current leakage dielectric medium is provided.

Abstract: The invention relates to a method of adjusting the edge angle of openings that are etched in a polysilicon layer.The steepness of the edge angles can be adjusted by means of a treatment of the polysilicon layer prior to the making of the photoresist mask with a mixture of 5 parts water and 1 to 3 parts ammonia and 0.25 to 1 part hydrogen peroxide. This pre-treatment is advantageously carried out at a temperature between 40.degree. and 70.degree. C.

Abstract: A novel substrate is disclosed which can mount either flip-chip solder bonded IC chips or wire bonded chips, or both chips, or a single chip having both solder bonds and wire bonds is disclosed. The substrate has an array of solder pads which will accept solder bonds. Those pads which are to be used for wire bonding have mounted thereon a trimetallic pedestal. Each pedestal has a layer of solder metal bonded to the solder pad, a top layer metal suitable for wire bonding, such as, aluminum or gold, and an intermediate layer of metal, such as nickel, which is impervious to both solder metal and the top layer metal.

Abstract: A method of treating ceramic materials used in semiconductor packaging applications to reduce their emission of alpha particles. Ceramic materials made of aluminum oxide particles bonded together with a siliceous binding material, are etched to remove the siliceous material from a surface portion of the ceramic. Since the typically used siliceous materials have alpha particle emitting elements in them by removing this siliceous material from a surface layer of the ceramic material the sources of alpha particles which are most likely to cause failures in electronic devices are removed. Alpha particle sources deeper in the ceramic pose a far lesser threat to the device because these relatively low energy, high volume particles suffer a substantial attenuation as they pass through aluminum oxide particles.

Abstract: A Schottky-barrier gate gallium arsenide field effect structure is made using a self-aligned gate fabrication technique. The resulting device includes source and drain regions, which are parts of a conducting channel formed through ion implantation or epitaxial growth or a combination of the two. A gate is formed on the same channel by first etching a portion of the channel between the source and the drain regions to form a gate window which then receives a Schottky-barrier gate electrode.

Abstract: There is disclosed an all silicon monolithic focal plane array of variable size infrared detectors for image detection. The structure comprises two epitaxial layers grown on an extrinsically doped silicon substrate. The detectors are formed in and extend through the substrate, the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The collection of charges takes place on a first buried layer formed around a portion of the first epitaxial layer-substrate interface, and the charges are then transferred through a third buried layer of the same conductivity type to a conducting surface layer on the upper portion of the second epitaxial layer. A second buried layer in a second portion of the epitaxial layer-substrate interface connected through a fourth buried layer to a surface layer provides a means for controlling the size of the detector region.

Abstract: There is disclosed a single crystal silicon charge storage apparatus suitable for use in an alternating current driven liquid crystal light valve. The charge storage medium is made of a high resistivity and photosensitive under AC excitation substrate on which an MOS capacitor is formed having fast photoelectric transient response and capable of operating over a wide frequency range. The AC activation provides to a liquid crystal light valve a greatly improved electrochemical stability. Electrically coupled high-reflectivity mirrors and light blocking layers can be used to couple the liquid crystal to the MOS capacitor.

Abstract: There is disclosed a single crystal silicon charge storage apparatus suitable for use in an alternating current driven liquid crystal light valve having therein a PIN photodiode structure. The charge storage medium is made of a high resistivity substrate on which an MOS capacitor is formed having fast photoelectric transient response an capable of operating over a wide frequency range. A PIN photodiode structure is provided on one side of the substrate next to the MOS capacitor to deplete the substrate of its mobile charge carriers during a portion of the AC cycle and to collect the electric field-guided signal representing charge carriers that are generated or introduced into the substrate by an input mechanism. The signal from the substrate is electrically coupled through high-reflectivity mirrors and light blocking layers to the liquid crystal.

Abstract: A non-volatile semiconductor storage device comprising a dual gate field effect transistor in which an electrically floating gate acts as a charge storage medium. An insulating layer of an appropriate dielectric material separates the floating gate from the active portion of the transistor. A predetermined section of this insulating layer is relatively thin to permit this section of the floating gate to be relatively close to a corresponding predetermined section of the transistor, thus facilitating the transfer of charges between the transistor substrate and the gate. When charges reach the floating gate either through tunneling or avalanche injection, they are entrapped and stored there, thus providing memory in the structure. That is, the electric field induced by these charges is maintained in the transistor even after the field inducing force is removed. Erasing is achieved by removing the charges from the floating gate by reverse tunneling through the relatively thinner insulator region.

Abstract: The specification describes a self-aligning masking technique for the fabrication of charge coupled device-metal oxide semiconductor (CCD/MOS) transistor combinations. Both the CCD devices and the output MOS transistors are formed on the same semiconductor substrate during the same processing steps. Two layers of polycrystalline silicon, isolated from each other by a layer of dielectric material and isolated from the semiconductor substrate by another dielectric layer are used to form two sets of partially overlapping semiconductor strips. These strips and predetermined portions of the substrate are then doped, with a conductivity determining impurity opposite the conductivity type of the substrate. This process produces two self-aligned sets of gate electrodes for a two-phase or a four-phase CCD device and also produces two output self-aligned gate field effect transistors at the end of the CCD array.