Abstract: Changing the locking mechanism in a U-lock, cable lock or other tie lock as often as desired is achieved without compromising the lock's resistance to physical damage. This function is achieved by an auxiliary sleeve that removably fits over the U-lock's crossbar or the cable lock's end bar. Either bar provides an aperture, which is too small to permit the locking mechanism to be picked or pried, but which is operatively positioned and sufficiently large to provide access for a key to the keyway of the locking mechanism.
Abstract: This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions.
Abstract: In a system for aligning successive configurations of minute semiconductors during manufacture, any selected configuration is carried on a precision X,Y,.theta. table, which is under the automatic control of (1) a standard television camera that is subject to conventional geometrical and shading distortions, (2) pattern-recognition and motor-control circuitry that corrects these distortions so that precision alignment is possible, and (3) a monitor including a television viewing screen for supervising the system.
Abstract: A microprocessor-based system serves as a message routing switch for communication between a number of different devices. Any device attached to the switch can communicate with any other attached device through a number of serial and parallel Input/Output ports. Communication between devices attached to the switch is in one of two formats. In a first method of communication, an attached device can be directly associated with another attached device in which case any communication from one is immediately transmitted to the other. In a second method of communication, an attached device communicates with the switch by means of fixed format packets, each of which contains a specification of its destination and error checking capabilities. This second method of communication permits examination of the validity of messages transmitted to or from the switch and enables message retransmission in the case of error.
January 21, 1977
Date of Patent:
November 13, 1979
Massachusetts Institute of Technology
David P. Misunas, Peter G. Jessel, Robert G. Jacobsen
Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor incorporates practical data-flow processing of a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnection that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.
Abstract: A digital computer may be structured in two separate sections, one of which performs the execution of arithmetic and conditional instructions, and the other which contains and performs operations upon data structures. The organization of the structure processing section of a digital computer is described herein. The structure processing section maintains data structures represented as acyclic directed graphs and is viewed as a functional unit by the instruction processing section; that is, instructions specifying structure operations are sent to the section, and any resulting values are returned to the instruction processing section. The organization of the structure processing section permits the simultaneous processing of many structure operations.
Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The processor operates in a data-driven fashion; that is, an instruction of a program in the processor is enabled for execution upon the arrival of all required operands, and upon being executed, sends copies of the resulting value to all instructions which require it for their execution. The processor incorporates a form of deadlock prevention between the instructions of a data-flow program, allowing a value to be generated by an instruction and sent to the successor instructions in the computation only when those instructions are ready to receive the value. The incorporation of this mechanism prevents the possibility of conflict between successive stages of a pipelined computation and between successive iterations of an iterative computation.
Abstract: Packet communication is used in the architecture of a memory system capable of processing many independent memory transactions concurrently. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.
Abstract: Packet communication is used in the architecture of a memory system having hierarchical structure. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.
Abstract: This invention is a new concept for the organization of digital data processing apparatus, suitable for highly parallel execution of certain computations involving repeated patterns of computational operations. Possible applications include many types of signal processing computations such as filtering, modulation and waveform generation. The invention permits exploitation of the unique properties of asynchronous digital logic.