Abstract: A content and collaborative filtering system for recommending entertainment oriented content items, such as music and video, and other media content items to a user based on similarity in profile between the user and other users and between the content indexed in the user's profile and other content in the database. The system stores implicit and explicit ratings data for such content items provided by the users. Upon request of the user, the system accesses the user's profile and corresponding content interests database. The system uses the relationships between the content items to determine a subset of the content items to be referred to the user. The system also correlates a similarity between the user's ratings of the content items and other users' ratings. Based on the correlations, a subset of users is selected that is then used to provide recommendations to the user. The recommended items have a high probability of being subjectively appreciated by the user.

Abstract: A device driver architecture that couples an operating system to a computer interface of a controller device that includes a plurality of functional sub-elements. The device driver includes a plurality of operating system interface objects each presenting an operating system interface (OSI) to the operating system, a plurality of computer interface objects each providing for the generation of programming values to be applied to the computer interface to establish the operating mode of a respective predetermined sub-element of the controller device, and a device driver library of processing routines callable by each of the plurality of operating system interface objects to process data and generate calls to the plurality of computer interface objects in predetermined combinations. The device driver library enables the selection of an execution contexts within which to define the generation and application of the programming values to the computer interface.

Abstract: Automatic generation of an application program is performed by a programmed system including a guided editor for establishing program, data and field definitions from a plurality of input event elements. A sequence generator, coupled to the guided editor, autonomously processes the program, data and field definitions into a plurality of functionally descriptive atomic sequences, each describing a unique characteristic such that a plurality of frames, each comprising zero or more functionally descriptive atomic sequences from each of the functionally descriptive sequences, respectfully describes the plurality of input event elements.

Abstract: A system is disclosed that includes a plurality of processors, which in some embodiments include DSPs and other microprocessors, and a distributed uniform memory. The distributed uniform memory is subdivided into a plurality of addressable memory spaces each of which are respectively primarily associated with one of the processors in the plurality of processors. At least an addressably contiguous portion of the addressable memory space primarily associated with one processor is mapped into the addressable memory space primarily associated with another processor. Thus, a processor will have access to the addressable memory space primarily associated with another processor, but will have such access independent of the load and timing requirements of the other processors.

Abstract: A system is disclosed that includes a first processor, which in some embodiments includes a DSP, and a first memory pool and a second memory pool. The second memory pool is primarily associated with the DSP and stores code that is available for execution by the DSP. A plurality of code modules are stored in the first memory pool, which in some embodiments is associated with a second processor. The code modules are individually and dynamically swapped into the first memory pool, which in some embodiments is not large enough to simultaneously store all of the code modules. In some instances, the dynamic code module swapping is done at the direction of a second processor, which is aware of the state of the DSP execution. In other instances, the dynamic code module swapping is done at the direction of the DSP. In each instance, dynamic code swapping is performed in a manner that minimizes or eliminates any halts in DSP instruction execution.

Abstract: A particular, appropriate BIOS extension image is selected from a potential set of multiple images for use in initializing a peripheral adapter. To enable proper selection, the peripheral adapter includes a firmware image of a BIOS extension that is storable on the peripheral adapter. The firmware image includes a nominal identifier of a BIOS extension and a set of one or more firmware markers that are compliant with the valid identification of the BIOS extension by a first predetermined host computer and that ensures that the firmware image is identifiable by a second predetermined host computer as being invalid. By specific selection of the firmware markers, these markers can be used to uniquely enable a predetermined one of the host processors to appropriately execute an appropriate BIOS extension image.

Abstract: An ESD protection circuit, suitable for use as part of an integrated circuit, limits the voltage potential at the contacts of the integrated circuit to a voltage potential difference range relative to, though extending beyond the voltage source potentials of the circuit protected. The ESD protection is effective regardless of whether the integrated circuit is powered. The ESD protection circuit includes a clamp subcircuit for limiting the voltage potential at a clamp point to a first voltage range approximately defined by the voltage source potentials and a voltage offset subcircuit, coupled between the clamp point and an integrated circuit contact, to establish a second voltage range encompassing the first voltage range. The voltage offset subcircuit conducts current between the clamp point and the contact to limit the voltage potential at the contact to the second voltage range.

Abstract: A graphics co-processor that is autonomously responsive to an instruction for the filling of a complex polygon, as defined by an enumeration of P vertices is described. The co-processor preferably includes a micro-engine sequencer and ALU (arithmetic logic unit) for selecting a first vertex from the enumeration of P vertices and for decomposing the complex polygon into a set of P-2 triangles, wherein each triangle includes the first vertex and to successive vertices as presented in the enumeration of P vertices is derived. A sense value is derived for each of the resultant P-2 triangles and each triangle is filled with a predetermined fill quantity that is qualified by the respectively associated sense value of the triangle being filled. Thus, the present invention provides for the autonomous execution of a fill polygon instruction for polygons having such complexities as concavities, self-intersections, overlapping sections and "holes".

Abstract: A charge pump circuit operates from a voltage provided on an input rail at a first potential relative to a reference potential rail and that provides second and third potentials relative to the reference potential rail on first and second output rails, respectively. The charge pump circuit includes first, second and third charge reservoir capacitors, an oscillator and control logic circuit for providing timing control signals, and a switch network responsive to the timing control signals for coupling the first, second and third capacitors in a plurality of configurations. The switch network also provides for the decoupling of the capacitors from between the input rail and the reference potential rail between transitions of these configurations.

Abstract: A code conversion system is described for converting a stream of data between first and second data codes. The stream of data containing data packets is recognized to be subject to a data fault condition arising from the collision of data packets. The conversion system comprises means for detecting the fault condition, and means for altering the code conversion of the stream of data between the first and second codes so as to reflect the occurrence of the fault condition in the code converted stream of data.

Abstract: An elastic buffer includes a memory array for storing received data, each location within the array having an associated cell storing a flag indicative of the most-recently performed (i.e., read or write) on the associated memory location. A potential write overflow of the memory is detected whenever a write attampt is made to a location whose flag indicates a write was most-recently performed. A potential read underflow is detected whenever a read attempt is made to a location when the flag associated with the location next to be read indicates a read was most recently performed. Also, a potential write operation of a memory location prior to the completion of a read on the next location within the array are also generates an overflow/underflow condition. Metastable logic state conditions within the array are avoided because the potential overflow/underflow conditions take cognizance of the finite propogation and setting times of signals within the array.

Abstract: A five volt only E.sup.2 PROM cell including metal bit read and bit ground column lines and polysilicon word select and program row lines. An interconnected word select and stacked gate transistor serially connect the bit read and bit ground lines. The cell also includes a tunneling structure, disposed below the program row line, for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line is disconnected from ground during the charging and uncharging operations.

Abstract: A master-slave flip-flop device wherein the master segment employs function and load isolated outputs driven in parallel with cross-coupled latch transistors is described. Signal feed forward may also be provided from a similarly isolated output of the master segment to a device output gate which also receives the otherwise final output of the slave segment. The device is found to exhibit a minimized duration of the undesired metastable state of the master segment and to, thereby, enhance propagation speed in which a stable state is established.

Abstract: A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.

Abstract: Negative working resists, prepared from poly(vinylpyridine) polymers which exhibit good sensitivities to 20 keV electron beam radiation, are disclosed. The poly(vinylpyridine) polymers of this invention may contain alkyl substituents on the pyridine rings in ortho, meta or para positions with respect to the nitrogen atom within said ring.

Abstract: A high frequency stripline-type power divider/combiner comprising a patterned metal layer having an input and two output strips, a dielectric substrate, and a resistive material layer interposed between the metal layer and substrate. A portion of the resistive material layer defines a resistive bridge that extends between and resistively interconnects the output strips, thereby acting as a resistive load for the cancellation of reflected power output signals. The patterned metal layer and resistive bridge are concurrently defined by standard photolithographic and etching techniques, thereby allowing the simple and accurate fabrication of an integral power divider/combiner.

Abstract: There is disclosed a single crystal silicon charge storage apparatus suitable for use in an alternating current driven liquid crystal light valve having therein a moderately doped microchannel stop grid. The charge storage medium is made of a high resistivity substrate on which an MOS capacitor is formed having fast photoelectric transient response and capable of operating over a wide frequency range. A doped microgrid structure is formed in one side of the substrate to prevent charge carrier spreading at the silicon-silicon dioxide interface and to provide a focusing electric field for the charge carriers. The signal from the substrate is electrically coupled through high-reflectivity mirrors and light blocking layers to the liquid crystal.

Abstract: A GaAs FET structure with a high electric field region, or active region, contacted by source, gate and drain electrodes is provided which can be used for high speed optical detection or for microwave oscillator optical injection locking. The device provides for efficient coupling of optical radiation into the active region through an opening in a semi-insulating substrate used to support the device. A buffer layer between the active region and the substrate prevents leakage current to the substrate, permits a larger illumination window for improved optical coupling and provides mechanical support for the FET detector. GaAs photodetectors are also provided by eliminating the gate electrode.

Abstract: An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type conductivity, respectively. Conventional source, drain and gate portions are formed in the regions and electrical contacts are made thereto. The improvement comprises providing self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity. The channel stops between regions of the opposite conductivity are mutually self-aligned. The self-alignment is achieved by use of a single mask, called a "complementary" mask. The process of the invention permits fabrication of submicrometer devices.

Abstract: A process is provided for fabricating a semiconductor device by thermal gradient zone melting, whereby metal-rich droplets such as aluminum migrate through a semiconductor wafer such as silicon to create conductive paths. One surface of the wafer in provided with a buffer layer thereon, which is placed directly on a heating surface. The buffer layer terminates the migration of the droplets to prevent alloying of the droplets with the heating surface.