Abstract: A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

Abstract: A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Abstract: A banking system is provided which is comprised of a central computer, a customer accounts main memory, and plural remote transaction terminals in communication with the central computer. Each remote terminal includes a cash dispensing apparatus, a personal identification number (PIN) signal generator, a random number (RN) signal generator, a security device and a cash dispenser. The communication paths from the RN and PIN signal generators to the security device are wholly contained within the remote terminal and inaccessible to would-be thieves. The remote terminals also include data entry devices activated by a customer to provide a PIN number, a PIN OFFSET number bearing a predetermined relationship to both the PIN number and a customer information file (CIF) signal stored in main memory, and other banking information. In response to a customer-initiated operation, a remote terminal supplies bank transaction and customer identification information to the central computer.

Abstract: A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses.The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

Abstract: A logic system requiring no tuning adjustments is provided for converting an MFM encoded information stream read from a mass storage medium to a non-return-to-zero (NRZ) information stream. The MFM encoded information stream is routed through an input shift register to provide plural information bit cells in parallel. Outputs of the shift register are sampled with a multiplexer to generate timing strobes for detecting an address mark, and for identifying clock bits, data bits and logic zero data appearing in the MFM encoded data field following the address mark. Clock bits are separated from the data, and both data bits and logic zero data are applied serially to an output shift register to form a serial NRZ data stream. Each time a data bit or logic zero data is loaded into the output shift register, a synchronization strobe is generated to transfer the NRZ data to succeeding systems.

Abstract: In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.

Abstract: A logic system is provided for precompensating data and clock bits of a formatted binary information stream during a modified frequency modulation (MFM) encoding for recording on a magnetic medium. The binary information stream is formatted into a gap field, an address preamble field, an address mark field and a data field. Clock bit generation is inhibited during the gap and address preamble fields. Further, a second of three clock bits occurring during the high order half-byte of the address mark field is suppressed to provide a modified MFM (M.sup.2 FM) field. An address mark is provided thereby for indicating the near proximity of a data field. Beginning with the low order half-byte of the address mark field, both MFM clock precompensation and MFM data precompensation is applied as required. The amount of peak shift occurring in the MFM encoded information stream after precompensation is substantially reduced.

Abstract: In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory.

Abstract: A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device.